Samsung Electronics Co Ltd v. Netlist Inc

1. Case Identification

• Case #: IPR2022-00639
• Patent #: 10,949,339
• Filed: March 2, 2022
• Petitioner(s): Samsung Electronics Co., Ltd.
• Patent Owner(s): Netlist, Inc.
• Challenged Claims: 1-35

2. Patent Overview

• Title: Memory Module with Controlled Byte-Wise Buffers
• Brief Description: The ’339 patent describes a computer memory module, such as a Dual In-line Memory Module (DIMM), that uses a series of data buffers distributed along its edge. These buffers manage data flow between a system’s memory controller and multiple ranks of memory devices on the module, creating what Petitioner describes as a "fork-in-the-road" data path architecture to improve signal integrity and performance.

3. Grounds for Unpatentability

Ground 1: Obviousness over Ellsberry and Halbert - Claims 1-35 are obvious over Ellsberry in view of Halbert.

• Prior Art Relied Upon: Ellsberry (Application # 2006/0277355) and Halbert (Patent 7,024,518).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Ellsberry discloses a memory module architecture that is remarkably similar to that of the ’339 patent. Ellsberry teaches an N-bit wide DIMM with a centralized controller for registering address and control signals, multiple ranks of DDR2 memory devices, and distributed byte-wide data buffers along the module’s edge. Crucially, Petitioner asserted that Ellsberry’s buffers create the same "fork-in-the-road" layout claimed in the ’339 patent, where the module controller directs data through the buffers to a selected "fork" (data path) corresponding to a specific memory rank, while other ranks receive no-operation (NOP) signals. Petitioner contended that Ellsberry discloses the core features of independent claims 1, 11, 19, and 27, including the module controller, byte-wise buffers, multiple memory ranks, and the data path structure.
  • To the extent that Ellsberry does not explicitly disclose the use of tristate buffers within its data path logic—a key limitation added during prosecution of the ’339 patent—Petitioner argued that incorporating them would be an obvious modification in view of Halbert. Halbert was presented as teaching the use of pairs of tristate buffers to interface with bidirectional data buses, a common technique to prevent bus conflicts and present a single, predictable electrical load to the memory controller. Petitioner mapped Halbert's teachings to claim limitations requiring logic to enable tristate buffers for specific time periods determined by latency parameters, consistent with standard JEDEC protocols for DDR memory.
  • Motivation to Combine: Petitioner asserted a POSITA would combine Ellsberry and Halbert to implement Ellsberry’s bidirectional drivers with the well-understood tristate buffer design taught by Halbert. The motivation would be to ensure reliable operation by preventing bus conflicts on shared bidirectional data paths and to reduce the electrical load on the system memory controller to a single, standard load per JEDEC specifications. This combination would be a straightforward application of known solutions to solve a known problem in memory module design. Power savings from driving data buses only during necessary intervals would provide additional motivation.
  • Expectation of Success: Petitioner argued that a POSITA would have had a high expectation of success. The combination involved applying standard, well-known tristate buffer circuits (Halbert) to a standard memory module architecture (Ellsberry) to achieve the predictable functions of load reduction and bus conflict avoidance.

4. Key Claim Construction Positions

• "Rank" and "Rank Select Signal": Petitioner argued these terms should be understood consistent with their use in JEDEC standards at the time, where a "rank" is a row of memory devices selected by a "chip-select signal." This construction was central to mapping Ellsberry's disclosure of selecting memory banks via chip-select signals to the claims.
• "Fork-in-the-road" vs. "Straight-line" Layout: Petitioner acknowledged that Patent Owner had previously tried to construe similar claims to cover a "straight-line" layout. However, Petitioner contended that it was unnecessary to resolve this dispute because Ellsberry discloses the same "fork-in-the-road" layout shown in the ’339 patent, rendering the claims obvious under either interpretation.

5. Arguments Regarding Discretionary Denial

• Arguments Against §314(a) Denial (Fintiv): Petitioner argued that discretionary denial under Fintiv was unwarranted. It stated that the co-pending district court cases were filed recently and concerned only infringement, not invalidity. Furthermore, no trial date was set, and no significant discovery had occurred, making it likely that a Final Written Decision (FWD) from the IPR would issue before any potential district court trial on invalidity.
• Arguments Against §325(d) Denial: Petitioner asserted that denial under §325(d) would be improper because the Examiner did not consider the primary asserted ground—the specific combination of Ellsberry in view of Halbert—during prosecution. Critically, Petitioner highlighted that the Examiner never addressed the Board’s FWD in a related IPR against a parent patent, which invalidated numerous similar claims based primarily on Ellsberry. Petitioner argued this constituted a material error by the USPTO, as the Examiner allowed claims despite a binding decision against patentably indistinct claims in a parent patent.

6. Relief Requested

• Petitioner requested the institution of an inter partes review (IPR) and the cancellation of claims 1-35 of Patent 10,949,339 as unpatentable.