Nokia Of America Corp v. TQ Delta LLC

1. Case Identification

• Case #: IPR2022-00678
• Patent #: 8,495,473
• Filed: March 10, 2022
• Petitioner(s): Nokia of America Corporation
• Patent Owner(s): TQ Delta, LLC
• Challenged Claims: 10-12, 19-21, 27-30, and 36

2. Patent Overview

• Title: Shared Memory for Interleaver and Deinterleaver
• Brief Description: The ’473 patent is directed to a multicarrier communications transceiver used in Digital Subscriber Line (DSL) technology. The invention focuses on efficiently managing memory by sharing a common memory between an interleaver and a deinterleaver and allocating portions of that memory based on communication parameters.

3. Grounds for Unpatentability

Ground 1: Claims 10-12, 19-21, 27-30, and 36 are obvious over Mazzoni in view of VDSL1.

• Prior Art Relied Upon: Mazzoni (Patent 7,269,208) and VDSL1 (ETSI TS 101 270-2).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Mazzoni taught the core limitations of the challenged claims, including a VDSL transceiver with a shared memory (MM) allocated between an interleaver (MET) and a deinterleaver (MDET) for upstream and downstream data paths. Mazzoni explicitly taught calculating the required memory size for each function based on parameters like impulse noise and data rate. However, Petitioner contended that Mazzoni did not expressly disclose transmitting or receiving a message during initialization to specify this memory allocation. This missing element was allegedly supplied by VDSL1, the official technical specification for VDSL systems. VDSL1 disclosed detailed initialization protocols, including a "channel analysis and exchange state" where transceivers negotiate operational parameters by exchanging messages (e.g., O-CONTRACTn). These messages contained the parameters (I and M) that define the interleaver memory size, thereby teaching the claimed message indicating how the shared memory is to be used.
  • Motivation to Combine: Petitioner asserted that a person of ordinary skill in the art (POSA) would be strongly motivated to combine these references. Both Mazzoni and VDSL1 are directed to VDSL systems. Mazzoni expressly stated its invention could be advantageously applied in a VDSL environment. A POSA implementing Mazzoni's transceiver would have naturally consulted the VDSL1 standard to ensure proper functionality and interoperability, particularly for standard procedures like initialization. The combination would allow Mazzoni's efficient memory architecture to function according to the standardized VDSL protocols.
  • Expectation of Success: A POSA would have had a reasonable expectation of success. Both references contemplated the same triangular implementation of convolutional interleaving and used the same fundamental parameters (I and M) to define the memory size, making the integration of VDSL1's initialization protocol into Mazzoni's system straightforward and predictable.

Ground 2: Claims 10-12, 19-21, 27-30, and 36 are obvious over VDSL1 in view of Fadavi-Ardekani.

• Prior Art Relied Upon: VDSL1 (ETSI TS 101 270-2) and Fadavi-Ardekani (Patent 6,707,822).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground presented an alternative combination where VDSL1 provided the foundational VDSL transceiver and its initialization protocols, but did not explicitly teach using a shared memory between the interleaver and deinterleaver. Petitioner argued that Fadavi-Ardekani supplied this missing element. Fadavi-Ardekani taught a DSL transceiver that utilized a shared Interleave/De-Interleave Memory (IDIM) in a "ping-pang fashion," where memory areas were alternately used by the interleaving and deinterleaving functions. Fadavi-Ardekani explicitly described an "optimal implementation" where a portion of the same memory must be used by both functions to process a communication session, thereby disclosing the claimed shared memory. The combination of VDSL1's standardized transceiver and initialization messages with Fadavi-Ardekani's shared memory architecture allegedly rendered the claims obvious.
  • Motivation to Combine: Petitioner argued that a POSA implementing the VDSL1 standard would seek to incorporate known efficiencies to reduce cost and hardware complexity, especially when supporting numerous symmetric and asymmetric data streams. Fadavi-Ardekani explicitly taught that its shared memory invention provided these benefits by reducing buffer size and integrated circuit area. Since both references were directed to DSL/VDSL technology, and Fadavi-Ardekani stated its invention could be implemented with VDSL, it would have been an obvious and advantageous design choice to combine them.
  • Expectation of Success: A POSA would have had a high expectation of success because both references addressed the same technical field (DSL transceivers) and disclosed compatible components, such as Reed-Solomon encoding and interleaving functions. The combination represented the application of a known efficiency-improving technique (shared memory from Fadavi-Ardekani) to a known system (the VDSL1 standard).

4. Arguments Regarding Discretionary Denial

• §325(d) - Same or Substantially Same Art: Petitioner argued against discretionary denial under §325(d), asserting that the presented grounds were materially different from the art considered during prosecution. Although Fadavi-Ardekani was before the Examiner, the rejection was overcome by adding limitations related to an initialization message. Petitioner contended that its grounds were new because they relied on VDSL1—a previously uncited reference—to expressly teach these very limitations, thus presenting the prior art in a new light and curing the deficiency identified by the Examiner.
• Fintiv Factors - Parallel Litigation: Petitioner argued against discretionary denial under the Fintiv factors. It asserted that the parallel district court litigation was in its nascent stages, with the claim construction hearing not scheduled until months after the IPR filing and the trial date over a year away and highly speculative. Petitioner emphasized the minimal investment of judicial resources in the district court case and stipulated that, if review were instituted, it would not pursue the same invalidity grounds in court, thereby favoring institution to streamline issues.

5. Relief Requested

• Petitioner requested institution of an inter partes review and cancellation of claims 10-12, 19-21, 27-30, and 36 of the ’473 patent as unpatentable.