Samsung Electronics Co Ltd v. Netlist Inc

1. Case Identification

• Case #: IPR2022-00711
• Patent #: 10,860,506
• Filed: March 22, 2022
• Petitioner(s): Samsung Electronics Co., Ltd.
• Patent Owner(s): Netlist, Inc.
• Challenged Claims: 1-20

2. Patent Overview

• Title: Memory Module with Timing-Controlled Data Buffering
• Brief Description: The ’506 patent discloses a memory module featuring memory devices, data buffers, and a module control device. The technology centers on determining a time interval based on signals received by a data buffer during a previous operation (e.g., a write or read leveling operation) and using that interval to delay a read strobe during a subsequent read operation to compensate for signal timing discrepancies.

3. Grounds for Unpatentability

Ground 1: Obviousness over Hiraishi and Butt - Claims 1-2, 4, 6-7, 11, 13-15, and 17-18 are obvious over Hiraishi in view of Butt.

• Prior Art Relied Upon: Hiraishi (Application # 2010/0309706) and Butt (Application # 2007/0008791).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Hiraishi disclosed the core elements of the challenged claims, including a memory module with a control device, memory devices, and data buffers. Hiraishi’s module performed "read leveling" to adjust signal timing, which included delaying a read strobe signal (DQS) to properly sample read data (DQ). The amount of this delay was determined based on signals received during the previous read leveling operation. Petitioner contended that to the extent Hiraishi’s disclosure on optimally sampling data was not explicit, Butt taught the precise details of calibrating a delayed read strobe signal to sample data at the ideal time within the "data eye."
  • Motivation to Combine: A POSITA would combine Butt’s detailed calibration and sampling methods with Hiraishi’s memory architecture to improve the reliability of high-speed data capture. Petitioner asserted that Butt provided a known, predictable solution to the exact problem Hiraishi’s read leveling circuit was designed to solve, making the combination a logical step to enhance system performance.
  • Expectation of Success: A POSITA would have had a high expectation of success because the combination involved applying a standard calibration technique from Butt to a conventional memory module architecture shown in Hiraishi, which was a straightforward and predictable engineering task.

Ground 2: Obviousness over Hiraishi, Butt, and Ellsberry - Claims 3, 5, 12, and 16 are obvious over Hiraishi and Butt in further view of Ellsberry.

• Prior Art Relied Upon: Hiraishi (Application # 2010/0309706), Butt (Application # 2007/0008791), and Ellsberry (Application # 2006/0277355).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground built upon the Hiraishi and Butt combination to address claims reciting specific memory device configurations, such as using pairs of 4-bit wide memory devices ("x4") instead of single 8-bit wide devices ("x8"). Petitioner argued that Ellsberry explicitly disclosed a memory module with a distributed buffer architecture similar to Hiraishi's and taught implementing it with either single x8 or pairs of x4 memory devices.
  • Motivation to Combine: A POSITA would combine Ellsberry’s teachings with the Hiraishi/Butt system because selecting between different memory device widths (e.g., x4, x8) was a common and standardized design choice at the time, often dictated by JEDEC standards. This was presented as a simple and predictable substitution of known components to meet design or supply chain needs, representing one of a finite number of design options.
  • Expectation of Success: The expectation of success was high, as it involved substituting one standard component configuration for another within a known architecture, a routine task for a memory module designer.

Ground 3: Obviousness over Hiraishi, Butt, and Kim - Claims 8-10 and 19-20 are obvious over Hiraishi and Butt in further view of Kim.

• Prior Art Relied Upon: Hiraishi (Application # 2010/0309706), Butt (Application # 2007/0008791), and Kim (Patent 6,184,701).

• Core Argument for this Ground:

  • Prior Art Mapping: This ground addressed claims requiring the detection and handling of signal "metastability." Petitioner contended that Hiraishi’s high-speed interface, which required precise alignment of clock and control signals, was susceptible to metastability. Kim was cited for its disclosure of a "metastability detection/prevention circuit" designed to be incorporated into circuits like data input buffers to solve this exact problem by generating metastability indicators.
  • Motivation to Combine: A POSITA would be motivated to integrate Kim's metastability detection circuit into the control logic of Hiraishi's data buffers. This would ensure the reliable capture of critical control signals, a known concern in high-speed memory systems. Kim provided an established solution to a known problem inherent in the Hiraishi system.
  • Expectation of Success: A POSITA would have expected success in combining the references, as it was a direct application of a known preventative circuit (Kim) to improve the robustness of a standard high-speed interface (Hiraishi).

• Additional Grounds: Petitioner asserted additional obviousness challenges based on combinations including Tokuhiro (Patent 8,020,022). These grounds argued for invalidity under a narrower claim interpretation where the "previous operation" for determining a read delay is specifically a write operation, a technique taught by Tokuhiro to improve efficiency.

4. Key Claim Construction Positions

• Petitioner argued that no claim terms required express construction for the Board to find the challenged claims unpatentable.
• For the purposes of the petition, Petitioner adopted the Patent Owner's position from parallel litigation that means-plus-function claiming under 35 U.S.C. §112, ¶6 does not apply to the claim terms.

5. Key Technical Contentions (Beyond Claim Construction)

• Petitioner structured its arguments around two alternative interpretations of the claims. The primary grounds (1-3) relied on a broader interpretation where the "previous operation" used to determine delay could be a read leveling or training operation. The additional grounds (4-6) relied on a narrower interpretation, consistent with the patent's specification, where the "previous operation" is a different memory operation (e.g., a write) whose timing is used to set the delay for a subsequent read operation.

6. Arguments Regarding Discretionary Denial

• Petitioner argued against discretionary denial under 35 U.S.C. §325(d), stating that the primary prior art reference (Hiraishi) and the asserted combinations were never presented to or evaluated by the examiner during prosecution.
• Petitioner also argued against discretionary denial under Fintiv, asserting that co-pending district court litigations were in their earliest stages, with no trial dates set, no discovery conducted, and invalidity not yet at issue. Therefore, the Board’s Final Written Decision would likely precede any substantive district court ruling on validity.

7. Relief Requested

• Petitioner requests institution of inter partes review and cancellation of claims 1-20 of the ’506 patent as unpatentable.