PTAB

IPR2022-00967

NXP USA Inc v. MediaTek Inc

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Key Events
Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Security Hardware for Controlling Access to Secured Assets
  • Brief Description: The ’451 patent discloses a system intended to resolve security deficiencies in computer architectures like the x86 environment. The invention uses dedicated "security hardware" to control access to "secured assets" based on an operating mode signal, such as a signal indicating the system has entered System Management Mode (SMM).

3. Grounds for Unpatentability

Ground 1: Claims 1-5 and 24-25 are obvious over Vu.

  • Prior Art Relied Upon: Vu (Application # 2001/0008015).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Vu discloses all limitations of independent claim 1. Vu teaches a method for computer security using a "secure processing mode" and an associated "secure memory." Petitioner mapped Vu’s Central Processing Unit (CPU) to the claimed "security hardware," its "secure mode interrupt" signal to the "operating mode signal," and its "secure memory" to the "one or more secured assets." In Vu, the CPU controls access to the secure memory, permitting access only when the CPU is in its secure processing mode, thereby meeting the core functional limitations of claim 1.
    • Prior Art Mapping (Dependent Claims): Petitioner asserted that the dependent claims are also obvious. The "bus interface logic" of claim 2 would have been an obvious and standard way for a POSITA to implement the disclosed connection between Vu's CPU and secure memory. The "system management mode" of claim 5 is explicitly disclosed by Vu as an example of a secure mode. Claims 24 and 25, which add a power port for reserve power, were argued to be obvious modifications, as a POSITA would have been motivated to adapt Vu's system for a portable computer, a common device that predictably used batteries and AC adapters for primary and reserve power.
    • Key Aspects: Petitioner contended that since Vu discloses every element of claim 1, the claim is anticipated, which is the "epitome of obviousness."

Ground 2: Claims 18-20 are obvious over Vu in view of Ahmed.

  • Prior Art Relied Upon: Vu (Application # 2001/0008015) and Ahmed (Patent 4,379,950).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground addresses claims 18-20, which add a "mailbox RAM" with an "inbox" and "outbox" to the device of claim 1. Petitioner argued that Vu provides the base system, as established in Ground 1. Ahmed discloses a "mailbox RAM" used in a microprocessor system to manage data interchange between components, specifically teaching separate memory sections for storing data in each direction of transmission, which function as an inbox and an outbox.
    • Motivation to Combine: A POSITA would recognize that Vu’s CPU and secure memory could operate asynchronously, which would create predictable data-transfer timing issues. The use of an intermediary buffer, such as the mailbox RAM taught by Ahmed, was a well-known technique for resolving timing issues between two asynchronous devices. Therefore, a POSITA would combine Ahmed's mailbox RAM with Vu's system to ensure reliable data transfer.
    • Expectation of Success: A POSITA would have a high expectation of success in this combination because it represented the application of a known solution (a mailbox RAM) to a known problem (asynchronous data transfer) to achieve a predictable result.

Ground 3: Claims 1-5 and 24-25 are obvious over Gephardt.

  • Prior Art Relied Upon: Gephardt (Patent 5,623,673).

  • Core Argument for this Ground:

    • Prior Art Mapping: Petitioner argued that Gephardt, like Vu, discloses a system that meets all limitations of claim 1. Gephardt describes memory mapping and locking to protect system management software from modification. Petitioner mapped Gephardt's "memory control unit" to the claimed "security hardware," its "MEMMODE" signal to the "operating mode signal," and its "system management memory space" to the "secured asset." In Gephardt, the memory control unit controls access to the secured memory space based on the MEMMODE signal, which indicates whether the system is in a normal or system management mode.
    • Prior Art Mapping (Dependent Claims): As with the Vu-based ground, Petitioner contended the dependent claims were obvious. The bus connecting the memory control unit and system memory meets the "bus interface logic" of claim 2. Gephardt’s operating mode is a "system management mode" (claim 5). The addition of power ports for a portable implementation (claims 24-25) was argued to be an obvious design choice for the same reasons articulated in Ground 1.

  • Additional Grounds: Petitioner asserted that claims 18-20 are also obvious over Gephardt in view of Ahmed. This argument relied on the same motivation to combine as in Ground 2: a POSITA would have been motivated to add Ahmed's mailbox RAM to Gephardt's system to resolve potential asynchronous data transfer issues between its memory control unit and system memory.

4. Relief Requested

  • Petitioner requests the institution of an inter partes review and the cancellation of claims 1-5, 18-20, and 24-25 of the ’451 patent as unpatentable.