PTAB

IPR2022-00999

Samsung Electronics Co Ltd v. Netlist Inc

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1. Case Identification

2. Patent Overview

  • Title: Flash-DRAM Hybrid Memory Module
  • Brief Description: The ’054 patent describes a memory module that includes a volatile memory subsystem (e.g., SDRAM), a non-volatile memory subsystem (e.g., NAND flash), and a controller. The module is designed to detect a power failure via a voltage monitor and, in response, use a backup power supply to transfer data from the volatile memory to the non-volatile memory for preservation.

3. Grounds for Unpatentability

Ground 1: Obviousness over Harris and FBDIMM Standards - Claims 1-3 and 15 are obvious over Harris in view of the FBDIMM Standards.

  • Prior Art Relied Upon: Harris (Application 2006/0174140) and the JEDEC FBDIMM Standards (EX1027-28).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Harris taught a memory module, specifically a Fully Buffered DIMM (FBDIMM), with an on-board voltage regulator module to convert an external voltage to appropriate local levels for its components, including DRAM devices and a buffer. The FBDIMM Standards specified the exact regulated voltages required for such a module, including 1.8V, 1.5V, and 0.9V. The combination of Harris’s regulator and the voltages from the FBDIMM Standards allegedly disclosed the core limitations of independent claim 1, including a voltage conversion circuit providing at least three regulated voltages. Petitioner contended that using well-known, high-efficiency buck converters to generate these step-down voltages was an obvious implementation detail for a person of ordinary skill in the art (POSITA). For claim 15, Petitioner argued that using a commercially available dual-buck converter to supply two of the required voltages was an obvious design choice to simplify the circuit and reduce component count.
    • Motivation to Combine: A POSITA would combine these references because Harris expressly disclosed its memory module was an FBDIMM. Therefore, a POSITA implementing Harris’s on-board voltage regulator would have been naturally motivated to consult the official FBDIMM Standards to determine the specific, standardized voltage levels required for the module's components.
    • Expectation of Success: A POSITA would have a high expectation of success, as the combination involved implementing a standard voltage regulation scheme on a standard memory module architecture according to its corresponding industry-published specifications.

Ground 2: Obviousness over Harris, FBDIMM Standards, and Amidi - Claims 1-30 are obvious over the combination of Ground 1 in view of Amidi.

  • Prior Art Relied Upon: Harris (Application # 2006/0174140), the JEDEC FBDIMM Standards, and Amidi (Patent 7,724,604).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground added the teachings of Amidi to the combination of Ground 1 to provide power failure detection and battery backup capabilities. Petitioner argued Amidi taught a power management block for a memory module that monitors the input voltage and, upon detecting a fault (e.g., undervoltage), switches to a battery backup to maintain the memory in a self-refresh state. Amidi’s power supervisory module allegedly met the limitations of claim 4, including a "voltage monitor circuit" that produces a "trigger signal" when the input voltage drops below a threshold, causing the module to transition to a second operable state (battery-powered self-refresh). For claim 6, which required overvoltage detection, Petitioner asserted this was an obvious extension, as Harris taught detecting tolerances of +/-15% and such dual-threshold monitoring was a common feature in commercially available power supervisor circuits.
    • Motivation to Combine: A POSITA would combine Amidi with the Ground 1 combination because Harris acknowledged concerns with power reliability and proposed a redundant power source. Amidi taught a specific, known technique (battery backup triggered by voltage monitoring) to improve the reliability of a similar device (a memory module), providing a clear motivation to incorporate its power management functionality into the FBDIMM of Harris.
    • Expectation of Success: The combination involved applying a known power backup solution to a standard memory module, a straightforward modification that a POSITA would expect to yield the predictable result of improved data integrity during power disruptions.

Ground 4: Obviousness over Spiers and Amidi - Claims 1-30 are obvious over Spiers in view of Amidi.

  • Prior Art Relied Upon: Spiers (Application 2006/0080515) and Amidi (Patent 7,724,604).

  • Core Argument for this Ground:

    • Prior Art Mapping: Petitioner argued that Spiers disclosed a backup device on a PCI card that was remarkably similar to the ’054 patent, teaching the core concept of a module with volatile SDRAM, non-volatile NAND flash memory, a processor, and a backup power supply (capacitors). Upon power failure detection, Spiers taught transferring data from the SDRAM to the NAND flash. The combination implemented Spiers using specific DDR2 or DDR3 SDRAMs and their corresponding standard operating voltages. Amidi was relied upon to provide further enabling details for the "voltage monitor circuit," teaching how to generate a "trigger signal" in response to the input voltage falling below a predetermined threshold.
    • Motivation to Combine: A POSITA implementing the general backup system of Spiers would be motivated to consult analogous art like Amidi to learn specific implementation details for power failure detection logic and voltage regulation, particularly as Spiers’s disclosure was not limited to a specific type of SDRAM or power monitor.
    • Expectation of Success: Success was expected because the combination involved implementing a known, specific power monitoring technique (from Amidi) into a compatible memory backup system (from Spiers) using standardized memory components (DDR2/DDR3 SDRAMs) and power converters.

  • Additional Grounds: Petitioner asserted an additional obviousness challenge (Ground 3) based on the Ground 2 combination further combined with Hajeck (Patent 6,856,556) to more explicitly teach both undervoltage and overvoltage detection. A final ground (Ground 5) added Hajeck to the Ground 4 combination for the same reason.

4. Arguments Regarding Discretionary Denial

  • Petitioner argued that discretionary denial under Fintiv was inappropriate. It asserted that two co-pending district court cases between the parties were in their infancy, with no trial dates set and no discovery requests served. The petition was filed less than one month after Petitioner was served with an amended complaint asserting the ’054 patent, demonstrating diligence and weighing against discretionary denial.

5. Relief Requested

  • Petitioner requested the institution of an inter partes review and the cancellation of claims 1-30 of the ’054 patent as unpatentable.