Samsung Electronics Co Ltd v. Netlist Inc

1. Case Identification

• Case #: IPR2022-01427
• Patent #: 9,318,160
• Filed: August 26, 2022
• Petitioner(s): Samsung Electronics Co., Ltd. and Samsung Semiconductor, Inc.
• Patent Owner(s): Netlist, Inc.
• Challenged Claims: 1-20

2. Patent Overview

• Title: Memory Package with Optimized Driver Load and Method of Operation
• Brief Description: The ’160 patent relates to memory packages with stacked memory dies. It discloses methods to reduce the electrical load on data drivers by using multiple drivers, with each driver communicating with a separate subset of the stacked array dies via distinct die interconnects.

3. Grounds for Unpatentability

Ground 1: Claims 1-20 are obvious over Kim in view of Rajan and Wyman.

• Prior Art Relied Upon: Kim (Application # 2011/0103156), Rajan (Patent 8,041,881), and Wyman (Patent 7,969,192).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Kim and Rajan are analogous arts that teach the foundational structure of the ’160 patent, including a memory package with stacked array dies, a control die, and die interconnects. Specifically, Kim was alleged to disclose stacked slave chips C1 and C2 (a "first group" and "second group" of array dies) connected to a main chip C0 (a "control die") via distinct through-silicon vias TSV1 and TSV2 ("first" and "second" die interconnects). Wyman was asserted to teach that signal paths of different lengths have different loads and require different drive strengths, and that using a full-capacity driver for a shorter path would be "wasteful" and "overkill."
  • Motivation to Combine: A POSITA would combine Kim and Rajan to create a memory package compatible with well-known JEDEC industry standards, which Rajan teaches. A POSITA would further incorporate the teachings of Wyman into the Kim/Rajan combination to improve power efficiency. Because Kim expressly shows that its TSV1 interconnect is shorter than its TSV2 interconnect, Wyman’s teaching would directly motivate a POSITA to use a smaller driver for the shorter path (TSV1) and a larger driver for the longer path (TSV2) to avoid wasteful power consumption.
  • Expectation of Success: Petitioner asserted that combining these known elements—a stacked chip structure (Kim), JEDEC interface standards (Rajan), and established principles of driver-load optimization (Wyman)—would yield the predictable result of a power-efficient, standards-compliant memory package.

Ground 2: Claims 1-20 are obvious over Riho in view of Rajan and Riho2.

• Prior Art Relied Upon: Riho (Application # 2011/0026293), Rajan (Patent 8,041,881), and Riho2 (Application # 2010/0195364).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner asserted that Riho, like Kim, discloses a memory package with a control chip and stacked SDRAM chips organized into distinct groups connected by through-silicon vias (TSVs) to reduce electrical load. Rajan was again relied upon for its teachings on making memory modules compliant with JEDEC standards and implementing features like rank multiplication. Riho2, which shares an inventor with Riho, was alleged to teach a circuit for optimizing output drive capacity to account for parasitic capacitance and resistance that vary based on a die's position within a stack.
  • Motivation to Combine: A POSITA would combine Riho and Rajan to ensure the resulting memory package conformed to JEDEC standards. A POSITA would be further motivated to combine this with Riho2. Since Riho acknowledges that manufacturing and positional variations within the stack affect TSV impedance, a POSITA would naturally look to the related Riho2 reference to solve this known problem. Riho2’s teaching to selectively activate drivers to achieve optimal strength for each data conduit provides a direct solution for improving efficiency and conserving power in Riho's design.
  • Expectation of Success: Petitioner contended that a POSITA would have a high expectation of success. Applying Riho2’s specific drive optimization techniques to account for the physical variations described in Riho was a straightforward application of known engineering principles to achieve the predictable benefit of improved power efficiency.

4. Arguments Regarding Discretionary Denial

• §325(d) Arguments: Petitioner argued that discretionary denial under §325(d) is unwarranted because the Examiner never considered the specific prior art references asserted in the petition (Kim, Rajan, Riho, Wyman, and Riho2). Although the Examiner reviewed a different reference by the same inventor as Rajan (Rajan137), it was not considered in combination with the other references asserted in the grounds, which allegedly cure the deficiencies the Patent Owner identified in Rajan137 during prosecution.
• Fintiv Arguments: Petitioner asserted that the Fintiv factors favor institution. A parallel district court case exists, but the petition was filed within three months of the ’160 patent being added to the litigation, meaning the court case is in its very early stages. Petitioner argued that the compelling merits of the petition weigh heavily in favor of institution.

5. Relief Requested

• Petitioner requests institution of an inter partes review and cancellation of claims 1-20 of the ’160 patent as unpatentable.