PTAB

IPR2023-00274

LzLabs GmbH v. IBM Corp

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Petition
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1. Case Identification

2. Patent Overview

  • Title: Emulation of Computer Instructions to Produce Condition Codes
  • Brief Description: The ’289 patent discloses a method for emulating the generation of condition codes from a source computer architecture (e.g., IBM z/Architecture) on a target computer with a different architecture (e.g., Intel IA32). The core technique involves generating a sequence of target machine instructions that directly calculates the appropriate condition code without using performance-intensive branch instructions.

3. Grounds for Unpatentability

Ground 1: Obviousness over Loderer - Claims 1, 4, 6, 10-11, and 16 are obvious over Loderer.

  • Prior Art Relied Upon: Loderer (European Patent Application EP0843256A2).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Loderer is directed to the same problem as the ’289 patent: emulating condition codes from a source machine (e.g., IBM/390) on a target machine (e.g., MIPS RISC) without using performance-degrading branch instructions. Loderer explicitly teaches generating a sequence of target machine instructions to calculate an emulated condition code. The method disclosed in Loderer involves setting an initial, provisional value for the condition code in a register (BM), generating "distinguishing information" in separate temporary registers (t1, t2) based on comparisons, and then using that information to modify the provisional value into the final condition code. This process, particularly the use of a provisional value modified by separate distinguishing information to avoid branches, was asserted to map directly to the limitations of independent claim 1 and its corresponding dependent claims. For example, Loderer’s use of shift instructions to modify the condition code based on the distinguishing information was argued to teach the claimed "direct calculation."

Ground 2: Obviousness over Loderer, PoO, and Kane - Claims 1-4, 6, 10-12, and 16-17 are obvious over Loderer in view of PoO, Kane, and the knowledge of a POSA.

  • Prior Art Relied Upon: Loderer (EP0843256A2), PoO ("Enterprise Systems Architecture/390 Principles of Operation," a 2003 IBM manual), and Kane ("MIPS RISC Architecture," a 1988 book).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground extended Loderer’s teachings to cover arithmetic instructions, such as an ADD instruction, which can result in an overflow condition. Loderer provides a detailed example for a COMPARE instruction but does not detail handling arithmetic overflows. Petitioner argued that PoO, an authoritative IBM manual, discloses the full IBM/390 instruction set and specifies that instructions like ADD use a unique condition code ("3") to signal a numeric overflow. Kane, a standard reference for the MIPS architecture (Loderer's target machine), teaches specific algorithms for detecting arithmetic overflow. While Kane's method uses branches, Petitioner asserted that a Person of Ordinary Skill in the Art (POSA) would have combined these references to implement a complete and accurate emulator.
    • Motivation to Combine: A POSA implementing Loderer's branchless emulation method for the entire IBM/390 instruction set would be motivated to consult PoO to understand all possible condition codes, including overflow. Loderer expressly states its technique is for "any instruction potentially influencing the value of the condition code." To handle the overflow condition on the target MIPS machine, the POSA would turn to a standard reference like Kane for overflow detection logic. The primary motivation would be to adapt Kane's branched algorithm into a branchless one, applying Loderer’s core teaching to gain the exact performance benefits Loderer describes. This would be a predictable extension of the disclosed concepts.
    • Expectation of Success: Petitioner asserted a POSA would have a reasonable expectation of success. The task involved modifying Kane's well-understood, bitwise logic for overflow detection to remove branches, a technique already demonstrated by Loderer for a different instruction type. This adaptation would involve applying routine programming skills to achieve a predictable result. The petition provided exemplary, non-branching MIPS instruction sequences to demonstrate how Kane's logic could be implemented using Loderer's principles.

4. Arguments Regarding Discretionary Denial

  • Petitioner argued that discretionary denial under §325(d) is unwarranted because the primary prior art references relied upon (Loderer, PoO, and Kane) were not considered by the Patent Office during the original prosecution of the ’289 patent.
  • Petitioner further argued that discretionary denial under §314(a) based on Fintiv factors would be inappropriate. The parallel district court litigation was in its infancy, with discovery not yet commenced and no trial date set. Petitioner asserted diligence in filing the petition after receiving infringement contentions and stipulated that, if the IPR is instituted, it would not pursue any invalidity ground in district court that was raised or could have been reasonably raised in the IPR.

5. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-4, 6, 10-12, and 16-17 of the ’289 patent as unpatentable.