Google LLC v. Singular Computing LLC

1. Case Identification

• Case #: IPR2023-00394
• Patent #: 10,754,616
• Filed: December 22, 2022
• Petitioner(s): Google LLC
• Patent Owner(s): Singular Computing LLC
• Challenged Claims: 1-5, 7-14, 16-22, and 24

2. Patent Overview

• Title: Computer Processors with Low Precision High Dynamic Range Elements
• Brief Description: The ’616 patent describes computer processors that use arrays of processing elements (PEs) to perform computations. The challenged claims are directed to a computing system with a host computer and a computing chip that includes a PE array with specific multiplier circuits adapted to receive and process floating-point values of particular bit-widths.

3. Grounds for Unpatentability

Ground 1A: Obviousness over Schmidt-2000 - Claims 1, 4-5 are obvious over Schmidt-2000.

• Prior Art Relied Upon: Schmidt-2000 (“KPROC - An Instruction Systolic Architecture for Parallel Prefix Applications,” a 2000 journal article).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Schmidt-2000 discloses a parallel computer on a single "KPROC-chip" with 1024 floating-point processors arranged in a 32x32 instruction systolic array. This system includes a host computer, an array of PEs (processors), local memory, arithmetic units, and I/O capabilities, meeting most limitations of claim 1. Schmidt-2000 uses a 16-bit architecture but explicitly states that an 8-bit architecture is "favourable" for image processing.
  • Motivation to Combine (for §103 grounds): This ground is based on a modification of a single reference. Petitioner asserted that a Person of Ordinary Skill in the Art (POSITA) would have been motivated to modify Schmidt-2000’s 16-bit architecture to an 8-bit architecture to create a coprocessor optimized for image processing. This modification is directly suggested by Schmidt-2000 itself and would have been a predictable design choice to reduce processor size and power consumption.
  • Expectation of Success (for §103 grounds): A POSITA would have a reasonable expectation of success in implementing an 8-bit version, as it involved reducing the width of existing hardware components, a routine task for an engineer. This modified 8-bit architecture would result in multiplier circuits that receive inputs with an 8-bit mantissa and an 8-bit exponent, thereby satisfying the bit-width limitations of claim 1 (mantissa ≤ 11 bits, exponent ≥ 6 bits).

Ground 1B: Obviousness over Schmidt-2000 and POSA Knowledge - Claims 7, 9, 14 are obvious over Schmidt-2000 in view of a POSITA’s background knowledge of semiconductor process advances.

• Prior Art Relied Upon: Schmidt-2000 and general knowledge of semiconductor scaling principles like Moore's Law.
• Core Argument for this Ground:
  • Prior Art Mapping: This ground addresses the limitation in independent claim 7 requiring "no less than 5000" PEs. Petitioner first contended this limitation lacks patentable weight as it represents a mere duplication of parts taught by Schmidt-2000. Alternatively, Petitioner argued that scaling the number of processors on a single chip was a well-known and predictable path to improving performance.
  • Motivation to Combine (for §103 grounds): A POSITA would combine the KPROC-chip architecture of Schmidt-2000 with well-established principles of semiconductor scaling to increase the number of PEs on a single chip. The motivation was the recognized performance benefit of using larger processor arrays for computationally intensive tasks, a concept explicitly acknowledged in Schmidt-2000.
  • Expectation of Success (for §103 grounds): A POSITA would have a high expectation of success. Based on Moore’s Law and documented advances in process node technology (e.g., from the 250-nm process used in Schmidt-2000 to 40-nm nodes available by 2009), a POSITA would have known that integrating well over 5000 PEs on a chip of the same size was achievable by the patent’s priority date.

Ground 3: Obviousness over Schmidt-2000, Schmidt-1999, and Kan - Claims 8, 10-13 are obvious over Schmidt-2000 in view of Schmidt-1999 and Kan.

• Prior Art Relied Upon: Schmidt-2000, Schmidt-1999 (a 1999 lecture note on a parallel video accelerator), and Kan (Patent 5,355,508).

• Core Argument for this Ground:

  • Prior Art Mapping: This ground targets claims requiring two distinct pluralities of processing elements with different capabilities. The scaled-up 8-bit KPROC array from Schmidt-2000 (per Ground 1B) serves as the "plurality of first processing elements." Kan teaches a hybrid processing system that combines a Single-Instruction, Multiple-Data (SIMD) unit with a Multiple-Instruction, Multiple-Data (MIMD) unit to accelerate a wider range of computations. The MIMD unit from Kan, with its 32-bit PEs, provides the claimed "plurality of second processing elements."
  • Motivation to Combine (for §103 grounds): A POSITA would combine these references to overcome the known limitations of using only a SIMD-type architecture (like Schmidt-2000's array), which is not well-suited for irregular computations common in image processing. Kan explicitly teaches combining architectures to create a more flexible and powerful coprocessor, providing a clear motivation to integrate a MIMD-type unit onto the Schmidt-2000 chip. Schmidt-1999, by the same authors as Schmidt-2000, provides details on implementing controllers for such arrays.
  • Expectation of Success (for §103 grounds): A POSITA would expect success in integrating these known architectural components onto a single chip using the advanced semiconductor processes available at the time.

• Additional Grounds: Petitioner asserted additional obviousness challenges, including combining Schmidt-2000 with Schmidt-1999 to add a control unit (Ground 2); combining Schmidt-2000 with Schimmler-1996 to create a multi-chip board implementation (Ground 4); and combining all primary references to meet further dependent claims (Ground 5).

4. Arguments Regarding Discretionary Denial

• Petitioner argued that discretionary denial under §314(a) or §325(d) is unwarranted. It contended that the primary prior art references (Schmidt-2000, Schmidt-1999, Kan, and Schimmler-1996) were not previously presented to the USPTO during prosecution and are not cumulative to the examined art. Furthermore, Petitioner noted that the only related litigation is in its infancy and that the Patent Owner had represented it would be voluntarily dismissed without prejudice.

5. Relief Requested

• Petitioner requests institution of inter partes review and cancellation of claims 1-5, 7-14, 16-22, and 24 of Patent 10,754,616 as unpatentable.