Google LLC v. Singular Computing LLC

1. Case Identification

• Case #: IPR2023-00395
• Patent #: 10,754,616
• Filed: December 22, 2022
• Petitioner(s): Google LLC
• Patent Owner(s): Singular Computing LLC
• Challenged Claims: 1-5, 7-14, 16-22, and 24

2. Patent Overview

• Title: Computing System with Processing Element Array
• Brief Description: The ’616 patent discloses a computing system featuring a computing chip with a large array of processing elements (PEs). The PEs are designed for parallel computations using low-precision, high-dynamic-range (LPHDR) floating-point values, and include specific arrangements of "edge" and "interior" PEs.

3. Grounds for Unpatentability

Ground 1A: Obviousness over Stuttard and Shirazi - Claims 1-5 are obvious over Stuttard in view of Shirazi.

• Prior Art Relied Upon: Stuttard (PCT Publication WO 2005/037326) and Shirazi (a 1995 IEEE Symposium proceeding).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Stuttard disclosed a Multi-Threaded Array Processing (MTAP) architecture with a scalable "poly" execution unit comprised of an array of PEs for high-performance parallel processing. This architecture mapped to the core components of independent claim 1, including the host computer, computing chip, and PE array with local memory and arithmetic units. However, Stuttard did not specify the bitwidth of the floating-point units in its PEs. Shirazi taught that for high-throughput applications like signal processing, using custom floating-point formats with reduced-bitwidth mantissas (e.g., 9 or 10 bits) and sufficient-width exponents (e.g., 6 or 7 bits) was advantageous. Shirazi explained this approach reduced chip area and power consumption compared to standard 32-bit formats without significant loss of precision. Petitioner asserted that implementing Shirazi’s reduced-bitwidth format in Stuttard's PEs would render the specific bit limitations of claim 1 (mantissa ≤ 11 bits, exponent ≥ 6 bits) obvious. Petitioner further argued that the claimed "edge" and "interior" PE layout was an obvious physical arrangement for a 2D array to reduce wiring length and improve chip aspect ratios.
  • Motivation to Combine: A POSITA would combine Stuttard and Shirazi to improve the efficiency of Stuttard’s parallel processor. Stuttard’s architecture was for "high performance, high data rate processing," and its performance scaled with the number of PEs. A POSITA would be motivated by Shirazi's teachings to use reduced-bitwidth floating-point units to make each PE smaller and more power-efficient, thereby allowing more PEs to be integrated onto a single chip to increase parallelism and overall performance.
  • Expectation of Success: A POSITA would have a reasonable expectation of success because Stuttard’s architecture was described as customizable and modular. Modifying the bitwidth of the floating-point units in the PEs to optimize for specific applications, as taught by Shirazi, was a known design trade-off and would involve applying predictable engineering principles.

Ground 1B: Obviousness over Stuttard and Shirazi - Claims 7-14 are obvious over Stuttard in view of Shirazi.

• Prior Art Relied Upon: Stuttard (PCT Publication WO 2005/037326) and Shirazi (a 1995 IEEE Symposium proceeding).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground built upon the Stuttard-Shirazi combination from Ground 1A to address the limitations of independent claim 7, which required "no less than 5000" PEs and a plurality of higher-precision "second processing elements" (the "mono" units from Stuttard). Petitioner contended that scaling the number of PEs was an obvious design choice driven by market demand for higher performance. Stuttard explicitly taught that its PE array could be scaled to "thousands of PEs." Petitioner argued that the specific number of 5000 was merely a result-effective variable, and achieving it would be a routine optimization based on available semiconductor process technology at the time (e.g., 40-nm and 32-nm nodes), which could accommodate billions of transistors. The "second processing elements" were mapped to Stuttard's "mono" execution units, which Stuttard taught could be more complex (e.g., 32-bit) than the "poly" PEs.
  • Motivation to Combine: The motivation was to maximize computational performance. For applications like image retrieval, performance is directly related to the number of parallel PEs. Stuttard's inventors and other prior art recognized the "unstoppable trend to put more and more cores on a single die." A POSITA would thus be motivated to scale the number of reduced-bitwidth PEs from the Stuttard-Shirazi combination to the maximum number feasible with contemporary fabrication technology, which easily exceeded 5000.
  • Expectation of Success: Success was reasonably expected because Stuttard's architecture was designed for "easy scalability." Furthermore, by 2009, advances in semiconductor fabrication had demonstrated the ability to place over 4 billion transistors on a chip, which was more than enough to implement over 5000 of the proposed PEs.

Ground 1C: Obviousness over Stuttard and Shirazi - Claims 16-22 and 24 are obvious over Stuttard in view of Shirazi.

• Prior Art Relied Upon: Stuttard (PCT Publication WO 2005/037326) and Shirazi (a 1995 IEEE Symposium proceeding).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground addressed independent claim 16, which recited connecting multiple computing chips. Petitioner argued it was obvious to mount two or more of the Stuttard-Shirazi chips on a circuit board to further scale performance. Stuttard explicitly taught connecting its chips "from one chip to another" via external ports and mounting them on circuit boards. When two such chips are connected, a PE on the second chip becomes an "external edge processing element" relative to the first chip, meeting that limitation. Claim 17's "torus interconnect" was argued to be a well-known and obvious technique for connecting PEs at the edges of an array (or between chips) to improve data propagation efficiency.
  • Motivation to Combine: The motivation was again to increase computing power beyond what a single chip could provide. Connecting multiple accelerator chips on a single board was a conventional method for building more powerful systems. A POSITA would have been motivated to apply this known technique to the Stuttard-Shirazi processor to achieve even greater performance for demanding parallel computing tasks.
  • Expectation of Success: A POSITA would expect success because connecting multiple chips was a standard industry practice. Stuttard provided external ports specifically for this purpose, indicating the design contemplated multi-chip configurations.

4. Arguments Regarding Discretionary Denial

• Petitioner argued that discretionary denial under §314(a) or §325(d) was not warranted. It was asserted that the parallel district court litigation was in its infancy and the Patent Owner had represented it would soon be voluntarily dismissed. Further, the primary prior art reference, Stuttard, was not previously presented to or considered by the USPTO during prosecution, meaning the petition raised new, substantial questions of patentability.

5. Relief Requested

• Petitioner requested institution of inter partes review and cancellation of claims 1-5, 7-14, 16-22, and 24 of Patent 10,754,616 as unpatentable.