Google LLC v. Singular Computing LLC

1. Case Identification

• Case #: IPR2023-00396
• Patent #: 11,169,775
• Filed: December 22, 2022
• Petitioner(s): Google LLC
• Patent Owner(s): Singular Computing LLC
• Challenged Claims: 1-5, 7-14, 16-23

2. Patent Overview

• Title: Processor with Low Precision High Dynamic Range Processing Elements
• Brief Description: The ’775 patent relates to a computing system featuring a chip with a large array of processing elements (PEs). The system is designed for parallel computations using PEs that employ specific low-precision, high-dynamic-range floating-point formats.

3. Grounds for Unpatentability

Ground 1: Claims 1-2 and 5 are obvious over Schmidt-2000 in view of Kan.

• Prior Art Relied Upon: Schmidt-2000 (a 2000 journal article on parallel computing architecture) and Kan (Patent 5,355,508).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Schmidt-2000 disclosed the core architecture of a computing system with a host computer and a "KPROC-chip" containing a 1024-processor array. Petitioner asserted that a person of ordinary skill in the art (POSITA) would modify Schmidt-2000’s 16-bit architecture to a more favorable 8-bit architecture for image processing, a modification Schmidt-2000 itself suggested. This modification would meet the claimed floating-point format limitations (e.g., mantissa width of no more than 11 bits). Kan was cited for its teaching of a hybrid processing system that combines both SIMD-type (like Schmidt-2000’s array) and MIMD-type units to handle different computational tasks within a single application field efficiently.
  • Motivation to Combine: A POSITA would combine Kan’s MIMD-type unit with the modified 8-bit KPROC-chip to create a more versatile single-chip coprocessor. This combination would accelerate not only the large-scale parallel tasks suitable for the KPROC array but also the irregular or task-level parallel computations for which the MIMD unit is optimized, thereby improving overall performance for applications like image processing.
  • Expectation of Success: A POSITA would have a reasonable expectation of success integrating these elements on a single chip, given the well-understood principles of processor design and the significant advances in semiconductor fabrication technology available at the time of the invention.

Ground 2: Claims 3-4 and 7-14 are obvious over Schmidt-2000, Kan, Schmidt-1999, and a POSITA's background knowledge.

• Prior Art Relied Upon: Schmidt-2000, Kan, Schmidt-1999 (a 1999 conference paper), and knowledge of semiconductor process advances.
• Core Argument for this Ground:
  • Prior Art Mapping: This ground built upon the Schmidt-Kan combination by adding teachings from Schmidt-1999, a paper by the same authors as Schmidt-2000. Schmidt-1999 disclosed a similar processor array that included an on-chip controller for issuing instructions and an on-chip cache to reduce off-chip I/O, which Petitioner mapped to the "control unit" and "instruction memory" limitations of claims 3 and 4. For claims 7-14, Petitioner addressed the limitation of "no less than 5000" PEs by arguing it was obvious to scale up the number of processors based on predictable technological advancements.
  • Motivation to Combine: The motivation to add a controller and cache from Schmidt-1999 was to adopt a conventional and more efficient design for managing the processor array and its data flow. A POSITA would be motivated to scale the number of PEs beyond 5000 to leverage the increased transistor densities afforded by newer semiconductor process nodes (e.g., 40-nm). This scaling was a direct and obvious path to achieving higher computational performance, a primary goal in the field.
  • Expectation of Success: The petition provided detailed analysis showing that, due to Moore's Law and process node scaling from 250-nm (used for Schmidt-2000) to 40-nm (available by 2009), transistor densities had increased by over 50 times. This would have allowed a POSITA to easily integrate well over 5000 8-bit processors onto a single chip of a similar size.

Ground 3: Claims 16 and 23 are obvious over Schmidt-2000 in view of Schimmler-1996.

• Prior Art Relied Upon: Schmidt-2000 and Schimmler-1996 (a 1996 conference paper).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground addressed claims reciting a circuit board comprising a "plurality of processing element arrays." Petitioner pointed to Schmidt-2000's disclosure that its architecture was "modular" and suitable for "building large arrays of many KPROC chips." Schimmler-1996, which was co-authored by one of Schmidt-2000's authors and cited within it, explicitly taught the conventional method of building a larger processor array by tiling multiple processor chips on a single circuit board.
  • Motivation to Combine: When single-chip integration limits were reached, a POSITA would have been motivated to follow the conventional approach taught by Schimmler-1996 to achieve even greater computational power. This involved placing multiple high-density processor chips (like the N-KPROC chips from Ground 2) on an add-on board to function as a powerful coprocessor for a host computer.
  • Expectation of Success: Assembling multiple chips on a circuit board was a well-established and predictable method for system scaling in the art.
• Additional Grounds: Petitioner asserted an additional obviousness challenge (Ground 4) for claims 17-22 based on a combination of Schmidt-2000, Schimmler-1996, Schmidt-1999, and Kan, which relied on similar arguments for combining a MIMD unit and on-chip controller onto chips that are then tiled on a circuit board.

4. Key Technical Contentions (Beyond Claim Construction)

• Petitioner's central technical contention was that the claim 7 limitation of "no less than 5000" processing elements (PEs) carries no patentable weight, arguing it is a mere duplication of parts that yields no new or unexpected result.
• In the alternative, Petitioner argued that scaling the processor array to well over 5000 PEs was obvious. This argument was supported by extensive evidence of predictable advancements in semiconductor manufacturing, including Moore's Law and the industry's progression to smaller process nodes, which would have enabled and motivated a POSITA to increase processor density to enhance computational performance.

5. Arguments Regarding Discretionary Denial

• Petitioner argued that discretionary denial under §314(a) or §325(d) is not warranted. The petition asserted that no prior proceeding had challenged the validity of the ’775 patent’s claims and that the parallel district court litigation was in its infancy and expected to be dismissed.
• Furthermore, Petitioner contended that the primary prior art references (Schmidt-2000, Schmidt-1999, Kan, and Schimmler-1996) were not previously presented to or considered by the USPTO during prosecution and are not cumulative of the examined art.

6. Relief Requested

• Petitioner requests institution of an inter partes review and cancellation of claims 1-5, 7-14, and 16-23 of the ’775 patent as unpatentable.