Google LLC v. Singular Computing LLC

1. Case Identification

• Case #: IPR2023-00397
• Patent #: 11,169,775
• Filed: December 22, 2022
• Petitioner(s): Google LLC
• Patent Owner(s): Singular Computing LLC
• Challenged Claims: 1-5, 7-14, 16-23

2. Patent Overview

• Title: Computer Processors and Other Devices Using Low Precision High Dynamic Range Values
• Brief Description: The ’775 patent describes computer processors that use low-precision, high-dynamic-range (LPHDR) processing elements (PEs) for computations. The claims are directed to a computing system with a chip comprising a heterogeneous PE array, where some PEs use reduced-bitwidth floating-point values and at least one other PE uses higher-precision values.

3. Grounds for Unpatentability

Ground 1: Obviousness over Stuttard and Shirazi - Claims 1-5 are obvious over Stuttard in view of Shirazi.

• Prior Art Relied Upon: Stuttard (WO 2005/037326) and Shirazi (a 1995 IEEE Symposium paper).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Stuttard disclosed a multi-threaded array processing (MTAP) architecture featuring a "poly" execution unit with many simple processing elements (PEs) and a "mono" execution unit with a more complex, scalar PE for non-parallel tasks. Stuttard taught that the mono unit’s ALU is likely "wider and more complex" than the poly unit ALUs. Shirazi taught that for high-throughput applications like signal processing, using custom, reduced-bitwidth floating-point formats (e.g., 10-bit mantissa, 7-bit exponent) saves chip area and power compared to standard 32-bit formats. Petitioner asserted that a POSITA would implement Stuttard’s numerous poly-unit PEs (the "first" through "fourth" arithmetic units) with multiplier circuits adapted for Shirazi’s reduced-precision formats (e.g., mantissa ≤ 11 bits, exponent ≥ 6 bits). The single, more complex mono unit would serve as the "fifth arithmetic unit" and would be implemented with a standard 32-bit multiplier to interface with a conventional host computer. The physical arrangement of PEs into a 2D array with edge and interior elements was argued to be a well-known and obvious design choice to reduce wiring length and signal delay.
  • Motivation to Combine: A POSITA would combine these references because Stuttard’s architecture is designed for the same high-performance, high-data-rate applications (e.g., FFT computations) that Shirazi addresses. Stuttard taught that performance derives largely from the number of PEs, not their individual power. Therefore, a POSITA would be motivated to use Shirazi's area-saving, reduced-precision formats for the numerous poly-unit PEs to fit more of them on a single chip, thereby increasing parallelism and overall performance while reducing cost and power consumption.
  • Expectation of Success: Petitioner contended a POSITA would have a reasonable expectation of success because Shirazi stated its custom formats were "feasible on CCMs" (custom computing machines), and Stuttard’s MTAP architecture is such a machine. Stuttard further taught its architecture was modular and customizable, explicitly noting that the poly and mono ALUs could differ in width and complexity. This inherent flexibility would have assured a POSITA that adapting the poly PEs to use Shirazi’s custom formats was a predictable and straightforward modification.

Ground 2: Obviousness over Stuttard and Shirazi with Scaling - Claims 7-14 and 16-23 are obvious over Stuttard in view of Shirazi.

• Prior Art Relied Upon: Stuttard (WO 2005/037326) and Shirazi (a 1995 IEEE Symposium paper).
• Core Argument for this Ground: This ground builds on the Stuttard-Shirazi combination by arguing it would have been obvious to scale the resulting processor to meet limitations such as having "no less than 5000" PEs (first processing elements) and a "plurality" of higher-precision PEs (second processing elements).
  • Prior Art Mapping: The base combination of Stuttard and Shirazi provides the heterogeneous architecture as described in Ground 1. To meet the limitations of the remaining claims, Petitioner argued that a POSITA would scale this architecture. This would involve replicating Stuttard's processor core—containing one mono unit and numerous poly units—multiple times on a single chip. For example, duplicating a core with 2048 poly PEs three times would result in 6144 reduced-bitwidth PEs and 3 full-precision mono units, satisfying the claim requirements for over 5000 "first" PEs and a plurality of "second" PEs. Similarly, placing two such scaled chips on a circuit board, as taught by Stuttard, would meet the limitations of claims 16-23.
  • Motivation to Combine: The motivation was driven by market forces and known design principles to increase computing performance. Stuttard itself taught that its processor "can scale with increasing function demands" and could consist of "thousands of PEs." A POSITA would recognize the clear benefit of increasing the PE count to improve performance for demanding applications like image retrieval. Duplicating an entire processor core is a conventional technique to scale performance while leveraging existing, proven designs, thereby saving cost and time. Further, having multiple mono units would allow for handling a wider range of tasks and more high-priority, non-parallel threads simultaneously.
  • Expectation of Success: Petitioner asserted a high expectation of success based on the rapid advancement of semiconductor fabrication technology. By the patent's priority date, 40-nm and even denser process nodes were available, allowing for the integration of over 4 billion transistors on a single chip. This was more than sufficient to fabricate a chip with over 5000 reduced-bitwidth PEs, as it represented a 100-fold increase in transistor budget compared to an earlier-generation 64-PE MTAP core that Stuttard’s applicant had demonstrated. The patent itself identified no special fabrication challenges, reinforcing that only ordinary skill was required for such scaling.

4. Arguments Regarding Discretionary Denial

• Petitioner argued that no basis exists for discretionary denial under §314(a) or §325(d). It was asserted that no prior proceeding had challenged the ’775 patent’s claims, the parallel district court litigation was in its infancy and the Patent Owner had indicated it would be voluntarily dismissed. Furthermore, the petition’s primary reference, Stuttard, had not been previously presented to or considered by the USPTO during prosecution.

5. Relief Requested

• Petitioner requests the institution of an inter partes review and the cancellation of claims 1-5, 7-14, and 16-23 of the ’775 patent as unpatentable.