Samsung Electronics Co Ltd v. Netlist Inc

1. Case Identification

• Case #: IPR2023-00455
• Patent #: 9,858,215
• Filed: January 10, 2023
• Petitioner(s): Samsung Electronics Co., Ltd.
• Patent Owner(s): Netlist, Inc.
• Challenged Claims: 1-29

2. Patent Overview

• Title: Memory Module with Rank Multiplication
• Brief Description: The ’215 patent describes memory modules and methods for improving performance and capacity through "rank multiplication." The technology uses logic circuitry to make multiple ranks of lower-density memory devices appear as a single, higher-density virtual rank to a memory controller.

3. Grounds for Unpatentability

Ground 1: Claims 1-29 are obvious over Perego in view of JESD79-2

• Prior Art Relied Upon: Perego (Patent 7,363,422) and JESD79-2 (a 2003 JEDEC standard for DDR2 SDRAM).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued Perego discloses a memory module with a buffer device that isolates multiple groups (ranks) of memory devices from a memory controller, similar to the ’215 patent. Perego’s buffer device receives and buffers command and address signals, is coupled between memory ranks and the memory bus, and includes logic for routing data to a selected rank while the other remains in standby. This, Petitioner asserted, maps to the core limitations of independent claim 1, including the register, buffer, logic, and rank-selection functions.
  • Motivation to Combine: A Person of Ordinary Skill in the Art (POSITA) would combine the teachings of Perego with the JESD79-2 standard because Perego explicitly discloses using DDR2 memory devices. JESD79-2 provides the standard specifications for operating such devices, including command protocols, timing, and signal definitions for read/write operations and data bursts. A POSITA would consult this standard to implement Perego’s flexible and upgradeable system with JEDEC-compliant DDR2 memory, yielding the predictable result of a functional, standards-compliant buffered memory module.
  • Expectation of Success: A POSITA would have had a high expectation of success, as the combination involved implementing a known module architecture (Perego) using industry-standard components and protocols (JESD79-2).

Ground 2: Claims 1-29 are obvious over Perego, JESD79-2, and Ellsberry

• Prior Art Relied Upon: Perego (Patent 7,363,422), JESD79-2, and Ellsberry (Application # 2006/0277355).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner contended that Ellsberry provides a detailed implementation of rank multiplication, where two smaller-capacity memory ranks emulate a single higher-capacity rank. Ellsberry’s control unit receives a single chip-select signal and generates separate, rank-specific chip-select signals to route data to the targeted rank while sending non-active commands (NOP/Deselect) to the non-targeted rank. This, combined with the base teachings of Perego and JESD79-2, allegedly renders all claim limitations obvious.
  • Motivation to Combine: A POSITA would combine Ellsberry with the primary references because Ellsberry is analogous art addressing the same problem of expanding memory capacity efficiently. Ellsberry’s detailed teachings on implementing rank multiplication with JEDEC-compliant devices provide a known, cost-saving technique that a POSITA would have been motivated to apply to Perego’s buffered memory module architecture. Both Perego and Ellsberry teach data buffering, making them known alternatives a POSITA would consider.
  • Expectation of Success: The combination would predictably result in a buffered memory module with a well-understood rank multiplication capability.

Ground 3: Claims 1-29 are obvious over Perego, JESD79-2, and Halbert

• Prior Art Relied Upon: Perego (Patent 7,363,422), JESD79-2, and Halbert (Patent 7,024,518).

• Core Argument for this Ground:

  • Prior Art Mapping: Petitioner argued Halbert is analogous art disclosing a memory module architecture with buffers that isolate memory devices from the capacitive loading of the system bus. Halbert teaches using separate data paths for different memory ranks (ranks 140 and 142) to avoid signal integrity issues, which Petitioner asserted is a key feature of the claimed invention. Halbert also teaches adding a one-clock-cycle delay to the overall CAS latency to account for the buffering.
  • Motivation to Combine: A POSITA would look to Halbert for its teachings on isolating memory devices and managing signal integrity in multi-rank modules, a known challenge. A POSITA would have been motivated to incorporate Halbert’s use of separate data paths and latency management into Perego’s architecture to improve performance and reliability, especially when implementing rank multiplication.
  • Expectation of Success: Combining these known techniques for buffering and rank management would have predictably improved the performance of a Perego-style module.

• Additional Grounds: Petitioner asserted an additional obviousness challenge (Ground 4) against claims 1-29 based on the combination of Perego, JESD79-2, and Matsui2 (Application # 2003/0039151). Matsui2 was cited for its teachings on external termination circuits to prevent signal reflection at high speeds, which Petitioner argued a POSITA would have been motivated to add to Perego’s module to ensure signal integrity.

4. Key Claim Construction Positions

• "rank": Petitioner proposed that a "rank" refers to "an independent set of one or more memory devices on a memory module that act together in response to command signals, including chip-select signals, to read or write the full bit-width of the memory module." Petitioner argued this construction is consistent with the patent’s specification and the understanding of a POSITA, who would recognize that terms like "bank" or "physical bank" were sometimes used synonymously.

5. Key Technical Contentions (Beyond Claim Construction)

• Effective Filing Date: Petitioner dedicated significant argument to establishing that the ’215 patent is not entitled to a priority date earlier than July 1, 2005. It argued that earlier-filed provisional applications failed to provide adequate written description under §112 for key limitations, such as providing different first and second control signals to a buffer to enable communication of distinct data bursts. This assertion is critical for establishing Ellsberry (filed June 1, 2005) as prior art for Ground 2.

6. Arguments Regarding Discretionary Denial

• Petitioner argued against discretionary denial under §325(d), contending that while some prior art was disclosed in an Information Disclosure Statement (IDS), it was "buried" among hundreds of references and there is no evidence the Examiner substantively considered the specific combinations asserted in the petition.
• Petitioner also argued against discretionary denial under Fintiv, stating the petition was filed promptly (within five months of the district court complaint) and that the parallel litigation was in its earliest stages, with a median time-to-trial that would not overlap significantly with the IPR proceeding.

7. Relief Requested

• Petitioner requests institution of an inter partes review and cancellation of claims 1-29 of Patent 9,858,215 as unpatentable.