PTAB

IPR2023-00464

Dell Technologies Inc v. Corrigent Corp

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1. Case Identification

2. Patent Overview

  • Title: Method for Self-Testing an Electronic System
  • Brief Description: The ’369 patent discloses a method for self-testing connections (lines or traces) within a modular electronic system, particularly one using a backplane. The method uses a "main module" with a switch to create a temporary "loopback" connection between two "subsidiary modules" to test an idle line without interrupting normal system traffic.

3. Grounds for Unpatentability

Ground 1: Obviousness over Ke and Lewis - Claims 1-26 are obvious over Ke in view of Lewis.

  • Prior Art Relied Upon: Ke (Patent 5,841,788) and Lewis (Patent 4,685,102).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Ke disclosed a modular electronic system for testing backplane interconnects, featuring a "bus master controller" (the '369 patent's main module) and multiple connected boards (subsidiary modules). Petitioner asserted that Lewis taught a "loopback" test circuit where a control processor and switch (a main module) establish a communication loop between two peripherals (subsidiary modules) to test idle communication links. The combination of Ke's backplane architecture with Lewis's loopback testing method allegedly rendered the challenged claims obvious.
    • Motivation to Combine: A POSITA would combine Ke and Lewis to gain the benefits of a well-known loopback test within the context of a configurable backplane system. Petitioner contended that a POSITA, faced with Ke’s highly configurable system, would be motivated to seek flexible and efficient testing methods like the one in Lewis. Furthermore, Lewis’s teaching of testing idle lines would have been a known and desirable way to test the backplane connections in Ke without disrupting active traffic.
    • Expectation of Success: Petitioner argued a POSITA would have a reasonable expectation of success because Ke itself acknowledged that multiple techniques for testing backplanes were known in the art. Implementing the specific loopback testing from Lewis in the Ke system was presented as a straightforward application of known testing principles to a known system architecture, using Ke's bus master controller to direct the test as taught by Lewis.

Ground 2: Obviousness over Cook and Lewis - Claims 1-26 are obvious over Cook in view of Lewis.

  • Prior Art Relied Upon: Cook (Patent 4,074,352) and Lewis (Patent 4,685,102).

  • Core Argument for this Ground:

    • Prior Art Mapping: Petitioner contended that Cook disclosed a computer system with multiple "line control processors" (LCPs), analogous to subsidiary modules, connected via a backplane to a "distribution card unit" (DCU) that functions as a main module and switch. As in the first ground, Lewis provided the specific loopback testing methodology. Petitioner argued the combination of Cook's backplane system with Lewis's loopback test disclosed all limitations of the independent claims, including using a main module to configure a test loop between two subsidiary modules.
    • Motivation to Combine: The motivation to combine Cook and Lewis mirrored the logic for combining Ke and Lewis. Cook disclosed a system with many different types of peripheral devices (card readers, printers, etc.), which would motivate a POSITA to seek adaptable testing configurations like Lewis's loopback test to verify connections between these varied components. Applying Lewis's inter-peripheral test to Cook's system was argued to be an obvious design choice for improving system reliability.
    • Expectation of Success: A POSITA would have an expectation of success because Cook already disclosed a "poll test" to check connections, demonstrating that testing was integral to the system. Petitioner asserted that applying a different but well-known testing technique from Lewis (loopback) to the Cook system would be a predictable modification, with the DCU in Cook being capable of controlling the test between specific LCPs.

  • Additional Grounds: Petitioner asserted additional obviousness challenges based on the combinations of Ke/Lewis/Sarkinen and Cook/Lewis/Sarkinen. Sarkinen (Application # 2003/0101426) was primarily cited to add teachings of network switches supporting multiple data formats and communication protocols (e.g., TDM and packet data) to address limitations in certain dependent claims.

4. Arguments Regarding Discretionary Denial

  • Petitioner argued that discretionary denial under Fintiv would be inappropriate because the co-pending district court litigations are in their early stages, with no trial dates set and key events like the Markman hearing yet to occur. The petition asserted that it raises unique issues and prior art combinations that narrow the issues for litigation.
  • Petitioner also argued against discretionary denial under 35 U.S.C. §325(d), contending that the arguments presented in the petition are not the same as or substantially similar to those previously presented to the USPTO. Specifically, the core prior art references of Lewis and Cook, and the specific combinations of Ke with Lewis or Cook with Lewis, were never before the examiner during the original prosecution.

5. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-26 of the ’369 patent as unpatentable.