PTAB

IPR2023-00754

Western Digital Technologies Inc v. Shamrock Innovations LLC

Title: Computing Module with Serial Data Connectivity
Brief Description: The ’675 patent discloses a bridge device to facilitate communication between two parallel data devices. The system is intended to be "transparent" to software by encoding, serializing, and echoing all configuration space accesses across a serial link connecting the devices.

Prior Art Relied Upon: Stewart (Patent 4,450,572).
Core Argument for this Ground:
- Prior Art Mapping: Petitioner argued that Stewart discloses every limitation of claim 7. Stewart describes an interface for asynchronous bit-serial communication between devices. It explicitly teaches a method of converting parallel data from a device into a serial format for transmission over a serial link using a parallel-to-serial register. Stewart further discloses receiving the serial data at a second device, where it is converted back into a parallel format. Critically, Petitioner asserted that Stewart’s use of a Manchester decoder, which "extracts the data signal... and a clock... signal from the information signals," directly teaches the limitation of "generating a first clock signal... using the second serial data," as construed by Petitioner.

Prior Art Relied Upon: Bryans (Patent 4,979,185).
Core Argument for this Ground:
- Prior Art Mapping: Petitioner contended that Bryans, which discloses a high bit-rate serial link, anticipates all elements of claim 7. The system in Bryans is preferably operated asynchronously and uses an encoder to convert a 16-bit parallel data word into a serial form for transmission over a fiber optic cable. The receiving end includes a decoder to convert the received serial data back into its original parallel form. Petitioner argued that Bryans' disclosure of a "clock recover circuit" that "extracts the clock from the data itself" and provides it to the decoder of the receiving module directly maps onto the claim's final limitation of generating a clock signal from the received serial data.

Prior Art Relied Upon: Onno (Patent 5,170,272).
Core Argument for this Ground:
- Prior Art Mapping: Petitioner argued that Onno, which details a broadband digital network based on asynchronous transfer mode, also anticipates claim 7. Onno’s system facilitates asynchronous serial communication between modules, teaching a parallel-series scrambler to convert parallel data to serial data for transmission. At the receiving end, a serial-parallel converter circuit transforms the received serial data back into parallel data. Petitioner asserted that Onno’s disclosure of a "clock module" that "recovers a clock signal... from the data in the receive direction" meets the final limitation of claim 7 by generating a clock signal for use by the receiving module directly from the received serial data stream.

"Generating a first clock signal, for use by the first module, using the second serial data": Petitioner argued that this phrase, added by amendment during prosecution without a clear antecedent basis in the specification, must be construed based on its plain language in the context of the art. Petitioner contended that a person of ordinary skill in the art (POSITA) would understand "generating a clock signal... using the second serial data" to include methods of producing a clock signal by acting upon the received serial data. This encompasses techniques common in the art, such as extracting or recovering an embedded clock signal from the serial data stream, a process taught by all three prior art references. This construction was central to all three anticipation grounds.

Petitioner presented substantial arguments that discretionary denial would be improper.
Denial under §314(a) (Fintiv): Petitioner argued against discretionary denial based on parallel litigation, asserting that the district court case was in its early stages with minimal investment by the parties. It was further argued that a final written decision (FWD) from the Board would likely issue before the estimated trial date, and that Petitioner would not pursue the same invalidity grounds in the litigation, thus avoiding overlap and promoting judicial efficiency.
Denial under §325(d): Petitioner argued that denial under §325(d) was unwarranted because the prior art references relied upon in the petition (Stewart, Bryans, and Onno) were never before the examiner during the prosecution of the ’675 patent. Petitioner contended that these references were not cumulative to the art of record and, with the benefit of an expert declaration, present teachings that the examiner did not previously consider.

Petitioner requests the institution of an inter partes review (IPR) and the cancellation of claim 7 of Patent 8,060,675 as unpatentable.