PTAB

IPR2023-00780

Intel Corp v. BiTMICRO LLC

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Key Events
Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Multi-Profile Memory Controller and Computing Device
  • Brief Description: The ’190 patent relates to memory controllers for solid-state storage devices that use "device profiles" containing memory attributes. The controller performs memory transactions on a memory store where different memory locations are associated with different profiles and their corresponding attributes.

3. Grounds for Unpatentability

Ground 1: Obviousness over Danilak and Cornwell - Claims 45-46, 51-54, 57, 59, 71-72, 76-77, 80, 82, 84-87, 92, and 95-98 are obvious over the combination of Danilak and Cornwell.

  • Prior Art Relied Upon: Danilak (Application # 2008/0086588) and Cornwell (Application # 2007/0180186).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Danilak disclosed a memory system with a flash interface circuit (a memory controller) that manages multiple physical flash memory devices and presents them to a host system as a single "virtual flash memory device." This controller can emulate attributes for the virtual device that differ from the underlying physical devices. However, Danilak lacked detail on the internal structure of its flash devices and how configuration data is stored and retrieved. Petitioner contended that Cornwell supplied these missing details. Cornwell disclosed a non-volatile memory device that stores its own attributes—such as device type, page size, and block size—in a dedicated "device data" area within the memory array. The combination of Danilak's controller architecture with Cornwell's self-describing memory devices allegedly disclosed the claimed memory controller that accesses a memory store where locations are associated with device profiles (Cornwell's stored device data) containing sets of attributes.
    • Motivation to Combine (for §103 grounds): Petitioner asserted multiple motivations for a person of ordinary skill in the art (POSITA) to combine the references. First, a POSITA implementing Danilak's system, which disclosed memory devices without structural detail, would have been motivated to look to references like Cornwell in the same field of memory management to provide a known, operational structure. Second, Danilak taught discovering configuration data from its memory devices but did not specify how; Cornwell taught the solution by describing the storage of this exact type of data within the memory device itself, making the combination necessary for full functionality. Third, both references contemplated using different memory types. Cornwell explicitly taught using "NAND and/or NOR flash media," and a POSITA would combine this with Danilak's system to leverage the well-known, complementary strengths of NOR flash (fast random access for code execution) and NAND flash (fast sequential writes for data storage) in a single, optimized system for portable devices.
    • Expectation of Success (for §103 grounds): Petitioner argued a POSITA would have had a reasonable expectation of success because the integration was a simple substitution of one known element (Cornwell's memory structure) for another (Danilak's generic devices), and the components used standard interfaces and performed operations in a predictable manner.

4. Key Claim Construction Positions

Petitioner argued that claim 45 includes nested means-plus-function limitations requiring construction. No other terms were argued to require construction.

  • "Means for Performing a Memory Transaction": Petitioner proposed the function is "performing a memory transaction" and the corresponding structure is the "memory controller" as depicted in the ’190 patent.
  • "Means for Addressing": Petitioner proposed the function is "addressing a first memory location," "obtain[ing] the first set of attributes," "us[ing] attributes from said first and second device profiles," and "select[ing] a transfer size." The corresponding structure was identified as the interface controller, memory device interface, and IO interface.
  • "Interface Controller Means": Petitioner proposed the function is "processing memory transaction requests" and the corresponding structure is an "interface controller."

5. Arguments Regarding Discretionary Denial

Petitioner presented substantial arguments that discretionary denial would be inappropriate under both §314(a) (Fintiv) and §325(d) (prior petitions).

  • Parallel Litigation (Fintiv): Petitioner argued the co-pending district court case is in its earliest stages, with no scheduling order issued and trial not expected until months after the Final Written Decision (FWD) in this inter partes review (IPR) would be due. Therefore, concerns of inefficiency and inconsistent rulings were minimal.
  • Prior Petition (General Plastic): Petitioner noted that while the ’190 patent was challenged in a prior IPR filed by Kioxia America, Inc., Intel has no significant relationship with Kioxia, was not involved in preparing that petition, and is accused of infringement based on different products. Petitioner further argued that its petition asserts different grounds, challenges additional claims, and was filed only nine days after the Kioxia IPR, weighing against denial.

6. Relief Requested

  • Petitioner requests institution of an IPR and cancellation of claims 45-46, 51-54, 57, 59, 71-72, 76-77, 80, 82, 84-87, 92, and 95-98 of the ’190 patent as unpatentable.