PTAB

IPR2023-00796

Apple Inc v. Lionra Technologies Ltd

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Key Events
Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Apparatus and Method for Baseband Beamforming, Carrier and Symbol Synchronization, and Data Demodulation
  • Brief Description: The ’141 patent relates to a beamforming transceiver architecture that processes transmit and receive signals for each antenna element individually at baseband. The system uses a single, shared baseband processor to perform these functions on a per-channel basis.

3. Grounds for Unpatentability

Ground 1: Obviousness over Williams and Fulton - Claims 1-4, 7-10, 18, 19, and 22 are obvious over Williams in view of Fulton.

  • Prior Art Relied Upon: Williams (Application # 2002/0042290) and Fulton (Patent 5,604,768).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Williams teaches a digital baseband beamforming system that meets most limitations of the challenged claims. Williams’s base transceiver station (BTS) includes an adaptive antenna array and a shared “digital array processor” that applies phase adjustments for both beamforming and hardware calibration to each digital baseband signal. This processor combines these adjustments into a single "net weighting factor" for each signal path. While Williams discloses combining beamforming and calibration adjustments, Petitioner contended it does not explicitly teach combining these with a carrier phase adjustment. To supply this element, Petitioner relied on Fulton, which discloses a radio system that uses a shared "rotator" to apply phase adjustments to digital baseband signals in both transmit and receive directions to correct for carrier phase offset (CFO).
    • Motivation to Combine: A POSITA would combine Fulton’s CFO correction with Williams’s system to improve signal accuracy and throughput, which are stated goals of both references. Petitioner asserted that correcting for CFO is a well-known technique to improve performance in wireless systems like the one disclosed in Williams. A POSITA would have recognized that Williams's system, which already corrects for internal phase errors via calibration, would be improved by also correcting for external phase errors (CFO) between the transmitter and receiver as taught by Fulton. The systems were argued to be compatible, as both operate on digital baseband signals to correct phase errors.
    • Expectation of Success: A POSITA would have a reasonable expectation of success in this combination due to the architectural similarities and the known, predictable benefit of CFO compensation. Petitioner argued that incorporating Fulton’s phase correction into Williams’s existing consolidated phase adjustment calculation would be a straightforward implementation of a known solution to a known problem.

Ground 2: Obviousness over Williams, Fulton, and Trott - Claims 20-21 are obvious over Williams in view of Fulton and in further view of Trott.

  • Prior Art Relied Upon: Williams (Application # 2002/0042290), Fulton (Patent 5,604,768), and Trott (Patent 6,836,673).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground builds upon the combination of Williams and Fulton from Ground 1 to establish the base apparatus of claim 1. It then introduces Trott to address the limitations of claims 20 and 21, which require the apparatus to be implemented as a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC)/very large scale integration (VLSI) circuit. Petitioner pointed to Trott’s disclosure that processor elements in an adaptive array beamforming system can be implemented as a "digital signal processor, general purpose microprocessor, FPGA, ASIC, a combination thereof, etc."
    • Motivation to Combine: A POSITA would have been motivated to implement the Williams/Fulton apparatus using an FPGA or ASIC as a standard design choice to achieve well-known benefits. Implementing the system as an FPGA would provide post-manufacturing reconfigurability, allowing for updates to new communications standards without new hardware. Alternatively, implementing it as an ASIC would yield significant advantages in decreased size, cost, and power consumption, along with increased performance compared to off-the-shelf processors.
    • Expectation of Success: Success would be predictable, as implementing processing systems on FPGAs or ASICs was a common and well-understood engineering practice at the time of the invention. This was merely the application of a known implementation technology to the otherwise obvious system of Williams and Fulton.

4. Arguments Regarding Discretionary Denial

  • Petitioner argued that the Board should not discretionarily deny institution under Fintiv. Petitioner stipulated that if the IPR is instituted, it will not pursue in a parallel district court proceeding the same grounds as in the petition or any grounds that could have reasonably been raised. Petitioner asserted that this Sotera stipulation, consistent with then-current USPTO guidance, resolves the Fintiv concerns and allows the Board to review the asserted grounds.

5. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-4, 7-10, and 18-22 of the ’141 patent as unpatentable.