Arista Networks Inc v. Corrigent Corp

1. Case Identification

• Case #: IPR2023-00837
• Patent #: 6,957,369
• Filed: April 18, 2023
• Petitioner(s): Arista Networks, Inc.
• Patent Owner(s): Corrigent Corporation
• Challenged Claims: 1-26

2. Patent Overview

• Title: Self-Testing Electronic System with Main and Subsidiary Modules
• Brief Description: The ’369 patent discloses a method and system for performing a "loop back" test on idle communication lines or traces within an electronic system. The system comprises a main module and multiple subsidiary modules connected via a backplane, allowing for the detection of hidden failures without interrupting normal data traffic on active lines.

3. Grounds for Unpatentability

Ground 1: Claims 1-26 are obvious over Ke in view of Lewis

• Prior Art Relied Upon: Ke (Patent 5,841,788) and Lewis (Patent 4,685,102).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Ke disclosed a system for testing interconnects on a backplane using a "bus master controller" (a main module) to test other boards (subsidiary modules) plugged into the backplane. Lewis disclosed a "loop back" system test circuit controlled by a processor and switch (a main module) to test links between peripherals (subsidiary modules), particularly when the links are idle. Petitioner asserted the combination taught all limitations of independent claim 1, including selecting a first idle line as an "aid line," a second idle line as a "test line," instructing one module to loop back traffic, configuring a switch to connect the lines, transmitting test traffic, and reporting a failure.
  • Motivation to Combine: A POSITA would combine Ke's backplane testing architecture with Lewis's loop back testing method for several reasons. Both references addressed testing connections in multi-component systems. A POSITA would have been motivated to incorporate Lewis's efficient loop back test into Ke's highly configurable backplane system to test connections between different boards. Furthermore, Lewis's teaching of testing lines when they are idle would be an attractive and obvious improvement to apply to Ke's system to avoid disrupting traffic, a known problem in the art.
  • Expectation of Success: A POSITA would have a reasonable expectation of success because Ke acknowledged that multiple techniques for testing backplanes existed, making the application of an alternative method like Lewis's straightforward. Ke's bus master controller, which already addressed and sent data to specific boards, could readily be adapted to manage the loop back testing between peripherals as taught by Lewis.

Ground 2: Claims 1-26 are obvious over Cook in view of Lewis

• Prior Art Relied Upon: Cook (Patent 4,074,352) and Lewis (Patent 4,685,102).

• Core Argument for this Ground:

  • Prior Art Mapping: Petitioner contended that Cook disclosed a digital computing system with multiple "line control processors" or LCPs (subsidiary modules) connected via a backplane. A "distribution card unit" or DCU, acting in concert with an Input-Output Translator (IOT), functioned as a switch and main module to manage communications between the LCPs. As in Ground 1, Lewis provided the specific loop back testing methodology for idle lines. Petitioner argued this combination met all limitations of the independent claims by using Cook's backplane architecture and implementing Lewis's method of selecting aid/test lines, creating a loop via the DCU/switch, and sending test traffic between LCPs.
  • Motivation to Combine: A POSITA would be motivated to combine these references for reasons similar to Ground 1. Both addressed testing in multi-component systems. Cook described a flexible system with many types of peripheral devices, making it an ideal candidate for improved testing configurations like the loop back test from Lewis. A POSITA would have sought to apply Lewis's method to Cook's architecture to test the connections between different peripherals on the backplane, especially when idle, to avoid disrupting busy lines, a concern noted in Cook.
  • Expectation of Success: A POSITA would have a reasonable expectation of success because Cook disclosed that its system could receive various "Test instructions," indicating that different testing techniques were interchangeable. The DCU/IOT in Cook, which already controlled communications and addressing for individual LCPs, could be easily adapted to implement the specific loop back testing protocol between two peripherals as taught by Lewis.

• Additional Grounds: Petitioner asserted that claims 3, 6, 8, 13, 14, 17, 21, 25, and 26 were also obvious over the combinations of Ke/Lewis and Cook/Lewis when further combined with Sarkinen (Application # 2003/0101426). Sarkinen was introduced to explicitly teach systems, such as network switches, that use multiple data formats and communication protocols (e.g., TDM and packet data), thereby rendering obvious the dependent claims reciting these features.

4. Arguments Regarding Discretionary Denial

• Petitioner argued against discretionary denial under §314(a) based on Fintiv factors, asserting that the parallel district court litigation was in its very early stages with no scheduling order or trial date set. Therefore, an FWD would likely issue long before trial, weighing against denial.
• Petitioner also argued that denial under §325(d) was inappropriate. While Ke was before the examiner during prosecution, the examiner never considered it in combination with Lewis. The Cook reference was never presented to the examiner at all. Therefore, Petitioner contended the core arguments and prior art combinations in the petition were not the same as, or substantially similar to, arguments previously considered by the USPTO.

5. Relief Requested

• Petitioner requests institution of an IPR and cancellation of claims 1-26 of the ’369 patent as unpatentable under 35 U.S.C. §103.