PTAB

IPR2023-01200

Western Digital Technologies Inc v. Longitude Licensing Ltd

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1. Case Identification

2. Patent Overview

  • Title: Data Sending/Receiving Operation Between Controller and Memory
  • Brief Description: The ’369 patent discloses a memory system comprising a controller and a memory that utilize strobe signals for data transfer. The system’s purported novelty resides in a read operation where the memory generates a "read data strobe signal" in direct response to receiving a "second data strobe signal" from the controller, and then transmits this generated signal back to the controller synchronized with the read data.

3. Grounds for Unpatentability

Ground 1: Obviousness over Lee - Claims 1, 6, 10, 14-19, and 25-27 are obvious over Lee.

  • Prior Art Relied Upon: Lee (Application # 2004/0022095).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Lee, which it characterized as describing "conventional" memory operations, discloses every element of the challenged claims. Independent claim 1 of the ’369 patent recites a system with a controller and memory performing distinct write and read operations. Petitioner asserted that Lee’s controller 140 sends a write data signal (DATA) and a strobe signal (SDtM, the claimed "first data strobe signal") to memory 120 during a write operation. For the read operation, Petitioner contended that Lee’s controller sends a strobe signal (SDtM, the claimed "second data strobe signal") to the memory to initiate a data read. Critically, Petitioner argued that Lee explicitly teaches that the memory 120 then "internally generates a third strobe signal SDfM [the claimed 'read data strobe signal'] in response to the received second strobe signal SDtM." This generated signal is then sent back to the controller along with the read data.
    • Key Aspects: Petitioner emphasized that Lee's disclosure of the memory generating a strobe signal responsive to a controller's strobe signal directly teaches the very feature that was added during prosecution to overcome a rejection and secure the patent's allowance. Petitioner asserted that Lee's description of this technique as conventional demonstrates its lack of novelty and obviousness.

Ground 2: Obviousness over Lee and JEDEC - Claims 2, 7, and 11 are obvious over Lee in view of JEDEC.

  • Prior Art Relied Upon: Lee (Application # 2004/0022095) and JEDEC (JESD79C Standard, Mar. 2003).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground targets dependent claims requiring the system’s controller to produce a clock signal that is independent of and separate from the data strobe signals. Petitioner argued that Lee discloses an asynchronous memory system where an intermittent strobe signal (SCA) is used to latch command and address information. In contrast, the JEDEC standard, which defines specifications for synchronous memory (DDR SDRAM), teaches using a continuous, free-running clock signal (CK) that is separate from the data strobe signal (DQS) to synchronize command and address signals. Petitioner asserted that the combination teaches all limitations of these dependent claims.
    • Motivation to Combine: A POSITA would combine Lee’s memory system with JEDEC’s standardized clocking scheme because it represented a simple substitution of one known element (Lee's intermittent SCA signal) with a known alternative (JEDEC’s continuous clock) to achieve predictable results. Petitioner argued that asynchronous and synchronous memory systems were well-known design alternatives with understood trade-offs. A POSITA seeking higher bandwidth and performance—a known advantage of synchronous systems—would have been motivated to replace Lee's intermittent, power-saving signal with the continuous clock taught by the JEDEC industry standard.
    • Expectation of Success: A POSITA would have a high expectation of success in making this combination. The modification involved implementing a heavily vetted, publicly available industry standard (JEDEC) into a conventional memory architecture (Lee). The result would be a predictable improvement in performance at the known cost of higher power consumption, representing a routine design choice rather than an inventive step.

4. Arguments Regarding Discretionary Denial

  • Petitioner argued against discretionary denial under the Fintiv factors, asserting that parallel district court litigation is in a very early stage, with cases stayed pending resolution of an action in which Petitioner is an intervenor and for which no trial date has been set. Petitioner further noted the minimal investment in the parallel proceedings and stated it would stipulate not to assert in court the same grounds on which the Board institutes an inter partes review (IPR).
  • Petitioner also argued that denial under 35 U.S.C. §325(d) based on the Advanced Bionics test would be improper. The petition relies on prior art references (Lee and JEDEC) that were not considered by the examiner during the original prosecution. Therefore, the challenges were argued to be non-cumulative, especially since Lee allegedly discloses the specific limitation upon which the examiner ultimately allowed the claims.

5. Relief Requested

  • Petitioner requests institution of an IPR and cancellation of claims 1-2, 6-7, 10-11, 14-19, and 25-27 of Patent 7,697,369 as unpatentable.