Western Digital Technologies Inc v. Longitude Licensing Ltd

1. Case Identification

• Case #: IPR2023-01286
• Patent #: RE43,539
• Filed: August 8, 2023
• Petitioner(s): Western Digital Technologies, Inc.
• Patent Owner(s): Longitude Licensing Ltd.
• Challenged Claims: 1-12

2. Patent Overview

• Title: Output Buffer Circuit
• Brief Description: The ’539 patent discloses an output buffer circuit designed to compensate for variations in power supply voltage and ambient temperature. The circuit comprises a main driver, a predriver, and a controller to maintain a predetermined output impedance and slew rate. A central feature is a predriver with outputs that drive only the first p-channel and first n-channel transistors of the main driver.

3. Grounds for Unpatentability

Ground 1: Obviousness over Itoh and Skorup - Claims 1-3 and 5-7 are obvious over Itoh in view of Skorup.

• Prior Art Relied Upon: Itoh (Patent 6,924,669) and Skorup (Patent 3,943,551).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Itoh disclosed a complete output buffer circuit with a main driver, predriver, and controller, meeting most limitations of the independent claims. Itoh's main driver included first and second pairs of PMOS and NMOS transistors for slew rate and impedance control, respectively. Itoh's predriver was shown to drive only the first pair of main driver transistors. Petitioner contended that the specific transistor configurations within Itoh's predriver logic gates (e.g., NAND gate 33, NOR gate 34) were not detailed. Skorup was introduced to supply these missing details, as it taught fundamental CMOS implementations of NAND and NOR logic gates using complementary pairs of PMOS and NMOS transistors connected in series and parallel.
  • Motivation to Combine: A POSITA would combine Skorup's fundamental teachings on CMOS logic gate implementation with Itoh's output buffer circuit. Because Itoh explicitly used CMOS technology and logic gates, it would have been a simple, predictable, and routine design choice to implement those gates using the well-known configurations taught by Skorup to achieve the known benefits of CMOS technology, such as high noise immunity and low power consumption.
  • Expectation of Success: A POSITA would have had a high expectation of success, as the combination involved applying basic, foundational CMOS circuit design principles from Skorup to the known circuit architecture of Itoh.

Ground 2: Obviousness over Itoh - Claims 1-8 are obvious over Itoh.

• Prior Art Relied Upon: Itoh (Patent 6,924,669).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner asserted that Itoh itself disclosed all elements of the challenged claims through a combination of its different embodiments. Itoh described two categories of embodiments: Category 1 (Embodiments 1-3) focused on output impedance control using additional pairs of output transistors, while Category 2 (Embodiments 4-5) focused on a different method of slew rate control. Petitioner proposed combining Itoh's Embodiment 2 (from Category 1) with Embodiment 4 (from Category 2). This combination allegedly resulted in a circuit where the slew-rate control predriver from Embodiment 4 drove the main driver from Embodiment 2, which included selectable pairs of transistors for impedance control.
  • Motivation to Combine: A POSITA would combine different embodiments from the same patent to leverage their respective advantages. Specifically, a POSITA would be motivated to combine the improved slew rate control taught by Itoh's Category 2 with the improved impedance control taught by Category 1 to create a single, optimized output buffer circuit with predictable and beneficial results. This was presented as a straightforward combination of disclosed features.
  • Expectation of Success: The combination of different but complementary embodiments within a single reference to achieve their stated individual benefits was argued to be a predictable design step for a POSITA.

Ground 3: Obviousness over Itoh and Muljono - Claims 1-8 are obvious over Itoh in view of Muljono.

• Prior Art Relied Upon: Itoh (Patent 6,924,669) and Muljono (Patent 6,288,563).

• Core Argument for this Ground:

  • Prior Art Mapping: This ground built upon the combination of Itoh's embodiments from Ground 2. Petitioner argued that while the combined Itoh circuit provided slew rate and impedance control, Muljono taught an explicit compensation circuit to make such controls independent of variations in process, supply voltage, and temperature (PVT). Muljono disclosed generating slew rate and impedance control signals in response to detected temperature and voltage variations. This compensation circuit and its control signals would be incorporated into the combined Itoh predriver and main driver circuits.
  • Motivation to Combine: Itoh and Muljono shared the goal of creating an output buffer with less variation. A POSITA reading Itoh would have been motivated to incorporate Muljono's well-known PVT compensation techniques to further improve the stability and performance of Itoh's circuit, achieving a more uniform output impedance and slew rate across different operating conditions.
  • Expectation of Success: A POSITA would have reasonably expected success in applying Muljono's established compensation methods to the known buffer architecture of Itoh to enhance its robustness against PVT variations.

• Additional Grounds: Petitioner asserted obviousness challenges against claims 9-12, which added a "delay monitor circuit." These grounds relied on combinations of Itoh, Skorup, and/or Muljono in further view of Borkar (Patent 4,975,598). Borkar was cited for its teaching of using a scaled-down version of an output driver as a delay monitor to dynamically compensate for PVT variations.

4. Arguments Regarding Discretionary Denial

• Petitioner argued against discretionary denial under Fintiv, stating that all related district court litigations were either in early stages with no trial date set or had been stayed. Petitioner further stipulated that it would not pursue in district court the same grounds on which the Board institutes an IPR, mitigating concerns of overlapping issues.
• Petitioner also contended that denial under §325(d) was unwarranted because the primary prior art references (Itoh, Skorup, Muljono, Borkar) were not considered by the examiner during prosecution. It argued these references were not cumulative and taught the claimed features, including the specific predriver connection that was the basis for the original patent's allowance.

5. Relief Requested

• Petitioner requested institution of an inter partes review and cancellation of claims 1-12 of Patent RE43,539 as unpatentable.