PTAB

IPR2024-00017

Cirrus Logic Inc v. Greenthread LLC

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: CMOS Semiconductor Device
  • Brief Description: The ’195 patent is directed to a Complementary Metal-Oxide Semiconductor (CMOS) device featuring graded dopant concentrations designed to aid the movement of minority charge carriers away from the device’s surface and into the substrate.

3. Grounds for Unpatentability

Ground 1: Obviousness over Payne - Claims 1-2 and 4-6 are obvious over Payne

  • Prior Art Relied Upon: Payne (Patent 4,684,971).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued Payne, which teaches an ion-implanted CMOS device, discloses or renders obvious every limitation of the challenged claims. Payne describes a "nested well structure" comprising a deep "tub region" (e.g., region 15) and a shallower "surface region" (e.g., region 18) formed within it. Petitioner asserted this structure maps directly to the ’195 patent’s claimed "single drift layer" (Payne’s tub region) and the "well region" (Payne’s surface region) disposed within the drift layer. Payne’s use of a "high-low implant profile" to form these regions results in a downward-sloping, graded dopant concentration extending from the surface layer to the substrate. Petitioner contended this graded profile inherently creates two distinct static unidirectional electric drift fields—a first field in the drift layer and a second field in the well region—that aid the movement of minority carriers toward the substrate, as claimed.
    • Key Aspects: For dependent claims, Petitioner argued Payne’s tub regions (e.g., 15) are deep wells formed by ion implantation extending 3-8μm deep, meeting the "deeply-implanted layer" limitation of claim 2. Petitioner also contended that Payne’s illustrative dopant profile includes segments that follow linear/quasilinear (claims 4-5) and exponential (claim 6) gradients, or that modifying Payne’s profile to achieve these well-known gradients would have been an obvious design choice.

Ground 2: Anticipation by Onoda and Obviousness over Onoda and Wolf - Claims 1-6 are anticipated by Onoda, or obvious over Onoda in view of Wolf

  • Prior Art Relied Upon: Onoda (Japanese Application H8-279598), Wolf (Wolf and Tauber, Silicon Processing, 2000).

  • Core Argument for this Ground:

    • Prior Art Mapping: Petitioner argued Onoda, which discloses a flash memory device, anticipates all challenged claims. A Person of Ordinary Skill in the Art (POSITA) would recognize Onoda’s device, which includes both NMOS and PMOS transistors and addresses latch-up, as a CMOS device. Onoda teaches forming a lightly-doped semiconductor layer (102) on a heavily-doped substrate (101) via epitaxial deposition. Petitioner mapped this layer 102 to the claimed "single drift layer." Within this drift layer, Onoda forms multiple P-wells and N-wells (e.g., P-well 105a), which meet the limitation of "at least one well region disposed in said single drift layer." Onoda’s fabrication process, involving ion implantation and thermal diffusion, results in a dopant concentration that "falls off smoothly," creating a downward-sloping graded concentration. Petitioner asserted this structure inherently generates the first and second static electric drift fields required by claim 1.
    • Motivation to Combine (for §103 ground): To the extent Onoda is not considered to explicitly disclose a CMOS device or a "deeply-implanted" layer, a POSITA would combine Onoda with the teachings of Wolf, a well-known textbook on semiconductor manufacturing. A POSITA would combine Onoda’s use of epitaxial layers with Wolf’s teachings on CMOS design to achieve known benefits such as lower power consumption and improved latch-up immunity. Specifically for claim 2, a POSITA would be motivated to use the high-energy "MeV implantation" taught by Wolf to form Onoda’s drift layer and wells, thereby creating a "deeply-implanted layer" while minimizing damage to near-surface structures, a key advantage described by Wolf.
    • Expectation of Success: A POSITA would have a reasonable expectation of success in combining these known semiconductor fabrication techniques to create Onoda’s structure with deep wells, as the processes were well-understood and would produce predictable results.

  • Additional Grounds: Petitioner asserted additional obviousness challenges, including claims 2 and 3 over Payne in view of Wolf (Ground IV) and claim 3 over Payne in view of Parrillo (Patent 4,435,896) (Ground V). These grounds relied on similar arguments, primarily proposing to modify Payne’s device using known techniques from Wolf or Parrillo to either form a deeply-implanted layer or fabricate the device on an epitaxial substrate to improve latch-up resistance.

4. Arguments Regarding Discretionary Denial

  • §314(a) / Fintiv: Petitioner argued that the Board should not exercise discretionary denial under Fintiv because the petition presents compelling evidence of unpatentability, particularly the single-reference obviousness ground over Payne. Petitioner also argued that the scheduled trial dates in the parallel district court litigations (February/March 2025) are close to or after the statutory deadline for a Final Written Decision (FWD), and that the litigations are in early stages with minimal investment of resources, weighing against denial.
  • §325(d): Petitioner contended that denial under §325(d) is unwarranted because the primary prior art references (Payne, Onoda, Wolf, Parrillo) were never presented to or substantively considered by the USPTO during prosecution of the ’195 patent. Petitioner specifically argued that Payne and Onoda are not cumulative to the cited reference Rhodes, because they teach a "nested-well" structure that is structurally and functionally distinct from the side-by-side well architecture taught in Rhodes.

5. Relief Requested

  • Petitioner requests institution of an inter partes review (IPR) and cancellation of claims 1-6 of the ’195 patent as unpatentable.