Cirrus Logic Inc v. Greenthread LLC

1. Case Identification

• Case #: IPR2024-00019
• Patent #: 11,316,014
• Filed: October 27, 2023
• Petitioner(s): Cirrus Logic, Inc.; OmniVision Technologies, Inc.; and AMS Sensors USA Inc.
• Patent Owner(s): Greenthread, LLC
• Challenged Claims: 1-9, 12-28

2. Patent Overview

• Title: Semiconductor Device with Graded Dopant Concentrations
• Brief Description: The ’014 patent is directed to an electronic system comprising a semiconductor device that utilizes graded dopant concentrations within its active and well regions to aid carrier movement and improve device performance.

3. Grounds for Unpatentability

Ground 1: Obviousness over Kawagoe - Claims 1-9, 12-14, 16-21, and 23-28 are obvious over Kawagoe.

• Prior Art Relied Upon: Kawagoe (Patent 6,043,114).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Kawagoe, a single reference, discloses all limitations of the challenged claims. Kawagoe teaches a twin-well CMOS device (Embodiment 4) and separately teaches fabrication on a uniformly-doped epitaxial substrate (Embodiment 1). The reference explicitly discloses forming graded dopant concentrations in the device’s well and channel regions that decrease with depth. This downward-sloping gradient creates a built-in electric field that sweeps charge carriers generated by alpha-particle strikes deep into the substrate, away from the active regions, thereby reducing soft errors and aiding carrier movement as claimed.
  • Motivation to Combine (within a single reference): A person of ordinary skill in the art (POSITA) would have been motivated to fabricate the twin-well CMOS device of Kawagoe’s Embodiment 4 using the uniformly-doped epitaxial substrate of Embodiment 1. The motivation stemmed from known trade-offs between manufacturing cost and latch-up resistance. Kawagoe itself explained that using the uniformly-doped substrate lowered manufacturing costs by half while still providing "excellent film quality" and improved device performance, making it an obvious design choice.
  • Expectation of Success: A POSITA would have had a high expectation of success because it involved a simple substitution of one substrate type for another, both of which were described in detail by Kawagoe for forming similar CMOS devices. The effects of such a substitution on device performance and cost were well-understood and predictable.

Ground 2: Obviousness over Wieczorek and Wolf - Claims 1-2, 4-9, 12-23, and 25-28 are obvious over Wieczorek in view of Wolf.

• Prior Art Relied Upon: Wieczorek (Application # 2003/0183856) and Wolf (Silicon Processing for the VLSI Era, 2000).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner asserted that Wieczorek described a conventional twin-well CMOS device with all the key features of the claims, including active regions, well regions, and a graded dopant profile that is highest at the surface and decreases with depth. This downward-sloping concentration aids carrier movement away from the surface, as claimed. While Wieczorek mentioned forming the device on an "appropriate substrate" without further detail, Wolf, a standard textbook on semiconductor manufacturing, taught that a uniform, lightly doped p-type or n-type substrate was a common and suitable choice for such twin-well CMOS devices.
  • Motivation to Combine: A POSITA, when implementing the conventional CMOS device described in Wieczorek, would have been motivated to consult a standard, authoritative textbook like Wolf to select a well-known and appropriate substrate. The combination was driven by the need to complete Wieczorek's disclosure with a standard, predictable component for its intended purpose.
  • Expectation of Success: Success was expected because the combination involved applying a standard substrate taught by Wolf to a conventional device structure taught by Wieczorek, a routine practice in semiconductor design that would yield predictable results.

Ground 3: Obviousness over Primary References and Gupta - Claims requiring a plurality of transistors are obvious over Kawagoe or Wieczorek-Wolf in view of Gupta.

• Prior Art Relied Upon: Kawagoe (Patent 6,043,114), Wieczorek (Application # 2003/0183856), Wolf (Silicon Processing for the VLSI Era, 2000), and Gupta (Patent 6,163,877).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground augmented the arguments from Grounds 1 and 2 by introducing Gupta to explicitly teach the limitations requiring a plurality of "transistors" or "devices" within an active region. Gupta is directed to automatically producing optimized layouts for CMOS circuits and explicitly teaches techniques, such as transistor chaining, to place the maximum number of transistors in an active region to minimize chip area and increase packing density.
  • Motivation to Combine: A POSITA would have been motivated to combine Gupta's layout optimization techniques with the CMOS fabrication processes of Kawagoe or Wieczorek-Wolf. This combination served the primary and well-known industry goal of minimizing semiconductor chip area to reduce cost and increase functionality.
  • Expectation of Success: There was a high expectation of success because Gupta’s layout rules were process-agnostic and designed to be applied to any CMOS semiconductor chip, including the conventional structures described in Kawagoe and Wieczorek-Wolf.
• Additional Grounds: Petitioner asserted additional obviousness challenges for claim 19 (image sensor) based on combinations of the primary references with Silverbrook (Patent 6,614,560).

4. Arguments Regarding Discretionary Denial

• Fintiv Factors (§314(a)): Petitioner argued against discretionary denial under Fintiv, asserting that the petition presents compelling evidence of unpatentability. It was noted that the scheduled trial dates in the parallel district court litigation (February/March 2025) occur after the statutory deadline for a Final Written Decision (FWD) in this inter partes review (IPR). Furthermore, discovery in the parallel cases was in its early stages, meaning significant judicial resources had not yet been invested.
• Advanced Bionics Framework (§325(d)): Petitioner contended that denial would be improper because the primary prior art references relied upon (Kawagoe, Gupta, Silverbrook, and Wolf) were not cited or substantively considered by the Examiner during the original prosecution. As the art and arguments were not previously before the Patent Office, the first prong of the Advanced Bionics framework was not met.

5. Relief Requested

• Petitioner requests institution of an inter partes review and cancellation of claims 1-9 and 12-28 of Patent 11,316,014 as unpatentable.