PTAB

IPR2024-00021

Cirrus Logic Inc v. Greenthread LLC

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1. Case Identification

2. Patent Overview

  • Title: CMOS Device Having Graded Dopant Concentrations
  • Brief Description: The ’222 patent is directed to a Complementary Metal-Oxide Semiconductor (CMOS) device with graded dopant concentrations in specific regions. The invention claims to use these graded concentrations to create static electric drift fields that aid the movement of charge carriers away from the device's surface layer into an area of the substrate without active regions.

3. Grounds for Unpatentability

Ground I: Claim 44 is obvious over Payne.

  • Prior Art Relied Upon: Payne (Patent 4,684,971).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Payne, which teaches a CMOS structure for high packing density, discloses every element of claim 44. Payne’s nested well structure, comprising shallow wells (e.g., region 18) formed within deep twin-wells or "tubs" (e.g., region 15), allegedly corresponds to the challenged claim’s limitations. Petitioner asserted that Payne’s deep tub region (15) is the claimed "single drift layer," and the shallow well (18) disposed within it is the claimed "well region." Furthermore, Payne explicitly teaches a "high-low implant profile" that creates a downward-sloping graded dopant concentration extending from the shallow well through the deep tub to the substrate.
    • Motivation to Combine (for §103 grounds): This is a single-reference ground. Petitioner contended that the graded dopant profile taught by Payne would have been understood by a Person of Ordinary Skill in the Art (POSITA) to inherently create the claimed first and second static unidirectional electric drift fields. Citing prosecution history from a parent patent, Petitioner argued the patent owner previously admitted that such downward-sloping profiles were known to create built-in electric fields that sweep minority carriers deep into the substrate, away from the active surface regions. Thus, all claimed elements were present in Payne, making claim 44 obvious.
    • Expectation of Success (for §103 grounds): A POSITA would have had a high expectation of success as Payne's disclosed structure and doping profiles would predictably result in the claimed electric fields and carrier movement.

Ground II: Claim 44 is anticipated by Onoda.

  • Prior Art Relied Upon: Onoda (Japanese Application H8-279598).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Onoda, which discloses a nonvolatile semiconductor storage device with improved latch-up resistance, anticipates every limitation of claim 44. Onoda’s structure is built on a P-type epitaxial layer (second semiconductor layer 102) formed on a heavily-doped P-type substrate (first semiconductor layer 101). Petitioner mapped this epitaxial layer 102 to the claimed "single drift layer." Within this layer, Onoda forms various P-type and N-type wells (e.g., third well region 105a). Petitioner mapped well region 105a to the claimed "well region disposed in the single drift layer." Onoda describes forming these regions via ion implantation and thermal diffusion, resulting in a dopant profile that "falls off smoothly" from the well region into the underlying epitaxial layer and toward the substrate. Petitioner asserted this smooth fall-off is the claimed graded dopant concentration, which inherently creates the required static electric drift fields for moving carriers into the substrate.

Ground III: Claim 44 is obvious over Onoda in view of Wolf.

  • Prior Art Relied Upon: Onoda (Japanese Application H8-279598) and Wolf (Silicon Processing, Lattice Press (2000)).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground was presented as an alternative to Ground II. Petitioner argued that if Onoda were deemed not to explicitly disclose a "CMOS" device as required by the preamble, its teachings would be combined with the Wolf textbook. Onoda discloses all the structural elements of the claim, including N-channel and P-channel transistors in its peripheral circuitry. Wolf was cited as a standard reference establishing that CMOS was the dominant, low-power silicon technology of the 1990s.
    • Motivation to Combine (for §103 grounds): A POSITA would combine Onoda's structure with Wolf's teachings on CMOS architecture to achieve a well-known benefit: reducing power consumption. A POSITA would have been motivated to implement the low-power CMOS architecture described in Wolf using the specific N-channel and P-channel transistors and manufacturing processes already disclosed in Onoda to improve its flash memory device.
    • Expectation of Success (for §103 grounds): Success would be expected because the combination involves implementing a standard, dominant device architecture (CMOS from Wolf) using known transistor types and fabrication techniques (disclosed in Onoda), which is a predictable engineering task.

4. Arguments Regarding Discretionary Denial

  • §314(a) (Fintiv Factors): Petitioner argued against discretionary denial under Fintiv, asserting the petition presents compelling evidence of unpatentability, including a single-reference obviousness ground and an anticipation ground. Petitioner further noted that parallel district court trial dates are scheduled after the statutory deadline for a Final Written Decision (FWD) in this IPR, and that discovery in those cases has not yet begun, meaning judicial resources have not been significantly invested.
  • §325(d): Petitioner argued against denial under §325(d), stating that the primary prior art (Onoda, Wolf) was never presented to the Patent Office during prosecution. While Payne was cited, it was not substantively considered or used as the basis for a rejection. Petitioner contended the Examiner erred by overlooking Payne's nested-well structure and its inherent properties, and instead erroneously identified a non-prior-art reference as the "closest reference." Therefore, the arguments and art are new and material to patentability.

5. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claim 44 of Patent 11,121,222 as unpatentable.