Cadence Design Systems Inc v. Semiconductor Design Technologies LLC

1. Case Identification

• Case #: IPR2024-00024
• Patent #: 7,971,167
• Filed: October 20, 2023
• Petitioner(s): Cadence Design Systems, Inc.
• Patent Owner(s): Semiconductor Design Technologies, LLC
• Challenged Claims: 1-4

2. Patent Overview

• Title: Semiconductor Design Support Device and Manufacturing Method of Semiconductor Integrated Circuit
• Brief Description: The ’167 patent discloses a methodology for semiconductor chip design using behavioral synthesis. The purported invention is the generation and use of a "correspondence table" to link blocks of high-level behavioral code to corresponding states in the lower-level register-transfer level (RTL) description, allowing latency information from RTL simulation to be correlated back to the original behavioral code.

3. Grounds for Unpatentability

Ground 1: Claims 1-2 are obvious over Harada and Gutberlet

• Prior Art Relied Upon: Harada (Application # 2006/0069538A1) and Gutberlet (WO 2005/119528A2).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Harada taught nearly all elements of the claims, including a semiconductor design support device that performs behavioral synthesis, generates an RTL description, and uses a "correspondence table" to link behavioral code (source lines) to RTL states. Harada’s latency analyzer calculated latency by counting the number of executions for each behavioral code block during a clock-based simulation. Petitioner contended that Gutberlet supplemented Harada by explicitly teaching the use of RTL logic simulation to calculate latency for each behavioral block in more specific units (e.g., clock cycles and nanoseconds) and reporting this data in a table.
  • Motivation to Combine: A POSITA would combine these references to improve Harada's known design process with Gutberlet's known latency analysis technique. Both references sought to debug behavioral code using latency analysis. Applying Gutberlet's method of reporting latency in clock cycles and nanoseconds to Harada's system would have been a predictable enhancement, as Harada already performed a clock-cycle-based simulation. The combination would provide designers with more convenient and detailed metrics to evaluate design choices.
  • Expectation of Success: A POSITA would have a reasonable expectation of success because the references described compatible techniques within the same field of behavioral synthesis. The combination involved applying known logic simulation and calculation methods to present additional, useful information for the shared purpose of debugging a design based on latency analysis.

Ground 2: Claims 1-2 are obvious over Ezaki, Gutberlet, and Shin

• Prior Art Relied Upon: Ezaki (Application # 2006/0225022A1), Gutberlet (WO 2005/119528A2), and Shin (CECS Publication TR03-42).

• Core Argument for this Ground:

  • Prior Art Mapping: Petitioner asserted that Ezaki, like Harada, taught a behavioral synthesis system that generates an RTL description and a "table of correspondence" to map between the behavioral and RTL descriptions for timing analysis. Gutberlet was added for its teachings on using RTL logic simulation to calculate latency in clock cycles for each behavioral block, reinforcing Ezaki’s latency analysis. Shin was introduced for its "state operations table," which provided a clear format for organizing and displaying behavioral code, corresponding RTL states, and associated delay information in a single, aligned view.
  • Motivation to Combine: A POSITA would be motivated to combine these teachings to create a more robust and user-friendly design tool. Gutberlet’s detailed simulation-based latency calculation was a known technique ready for improvement that could be directly applied to Ezaki's behavioral synthesis process. Shin's table format offered an improved method for visualizing the correlation between behavioral code and RTL latency data from the combined Ezaki/Gutberlet system. Ezaki itself suggested that "a variety of changes or substitutions" could be made to its process, motivating the inclusion of complementary techniques from Gutberlet and Shin.
  • Expectation of Success: Success was predictable because the combination involved integrating compatible and well-known techniques (logic simulation, latency analysis, correspondence tables) common in behavioral synthesis workflows. The teachings were complementary and did not change the fundamental principle of operation of any reference. Shin's teachings would facilitate the combination by providing a clear structure for presenting the correlated data.

• Additional Grounds: Petitioner asserted that claims 3-4, which add conventional integrated circuit manufacturing steps, are obvious over the combinations of Grounds 1-2 when further combined with Rittman (Application # 2002/0152453A1), which teaches standard manufacturing steps like layout and photomask creation. A similar ground for claims 3-4 was asserted based on the combination of Ground 2 and Rittman.

4. Key Claim Construction Positions

• "Block": Petitioner proposed that "block" means "a sequence of code surrounded by matching delimiters." This construction was argued to be supported by the specification and prosecution history, where blocks in the C language examples are delimited by curly braces ({}). This construction is important for identifying the discrete units of behavioral code in the prior art that are mapped to RTL states and for which latency is calculated.

5. Arguments Regarding Discretionary Denial

• Petitioner argued that discretionary denial would be inappropriate.
  • Against denial under Fintiv, Petitioner asserted that the parallel district court litigation was in its earliest stages, with no trial date set, no case schedule entered, and no claim construction briefed.
  • Against denial under §325(d), Petitioner argued that the primary references relied upon (Harada, Gutberlet, Shin, and Rittman) were never cited or considered during the original prosecution. While Ezaki was cited, the Examiner allegedly overlooked its teaching of a "correspondence table" and performed no substantive analysis of it, meaning the core arguments in this petition were not previously presented to the Office.

6. Relief Requested

• Petitioner requested institution of an inter partes review and cancellation of claims 1-4 of the ’167 patent as unpatentable.