NXP USA Inc v. Bell Semiconductor LLC

1. Case Identification

• Case #: IPR2024-00168
• Patent #: 7,345,245
• Filed: November 9, 2023
• Petitioner(s): NXP USA, Inc.
• Patent Owner(s): Bell Semiconductor, LLC
• Challenged Claims: 1-12

2. Patent Overview

• Title: Robust High Density Substrate Design For Thermal Cycling Reliability
• Brief Description: The ’245 patent discloses a semiconductor package design intended to improve reliability during thermal cycling. The invention addresses stress-induced cracking of signal traces by defining a "high stress zone" around the corner of a mounted integrated circuit die and routing all signal traces on a bottom routing layer outside of this specified zone.

3. Grounds for Unpatentability

Ground 1: Obviousness over Devnani and AAPA - Claims 7-8 and 10-11 are obvious over Devnani in view of Applicant's Admitted Prior Art (AAPA).

• Prior Art Relied Upon: Devnani (Application # 2003/0183919) and AAPA.
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Devnani disclosed a conventional multi-layer semiconductor package comprising all the basic structural elements of independent claim 7, including a top layer with a mounted die, a plurality of layers underneath, a bottom routing layer with signal traces, and a ball pad layer. Petitioner asserted that the final limitation—routing traces away from a high-stress area defined by the die corner—was taught by the AAPA. The AAPA, described in the ’245 patent’s own background section, acknowledged the known problem of trace cracking near die corners and described an existing solution of defining a circular "keep-out" zone where traces were not routed.
  • Motivation to Combine: A Person of Ordinary Skill in the Art (POSITA) would have been motivated to apply the known technique from AAPA to the conventional package of Devnani for the predictable purpose of improving reliability. The motivation was to solve the well-documented problem of trace cracking caused by thermal stress concentrated at the die corners.
  • Expectation of Success: A POSITA would have had a high expectation of success because the combination involved applying a known solution to a known problem within the same field of art, yielding only predictable results.

Ground 2: Obviousness over Devnani, AAPA, and Pillai - Claim 9 is obvious over Devnani in view of AAPA, and further in view of Pillai.

• Prior Art Relied Upon: Devnani (Application # 2003/0183919), AAPA, and Pillai (Patent 6,680,530).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground built upon the Devnani and AAPA combination to address dependent claim 9, which added the limitation that there are "no metal traces on the ball pad layer which are connected to the ball pads." Petitioner contended that Pillai taught this feature by disclosing a package design where vias, rather than surface traces, were used to connect ball pads on the bottom layer to routing layers above.
  • Motivation to Combine: A POSITA seeking to further enhance the reliability of the package taught by Devnani and AAPA would have been motivated to incorporate Pillai’s design. Using vias was a common technique that would reduce the risk of damage to metal traces on the exposed ball pad layer during thermal cycling, thereby improving the overall robustness of the package.

Ground 7: Obviousness over Chung and Celeron - Claims 1, 2, and 5 are obvious over Chung in view of Celeron.

• Prior Art Relied Upon: Chung (Application # 2003/0003705) and Celeron (a 2003 datasheet for the Mobile Intel® Celeron® Processor).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Chung disclosed the primary structure of independent claim 1: a semiconductor package with a top layer, a die with a corner, a multi-layer structure, a bottom routing layer, and a ball pad layer. To meet the limitation of keeping signal traces and ball pads away from the die corner by a distance of "two ball pad pitches," Petitioner relied on Celeron. The Celeron datasheet provided detailed mechanical specifications for a commercial processor package, explicitly showing a "clear area" or "keepout zone" on the bottom surface that was devoid of ball pads. Petitioner’s analysis of the Celeron specifications demonstrated that this clear area extended more than two ball pad pitches from the die corner.
  • Motivation to Combine: A POSITA designing the package taught by Chung would have been motivated to incorporate the defined keep-out zone from the Celeron datasheet. Both references were in the same field, and implementing such a clear area was a known method to prevent solder ball bridging and mitigate thermal stress effects, thus improving manufacturability and reliability.
• Additional Grounds: Petitioner asserted numerous other obviousness challenges, including combinations using Devnani or Chung with Tanahashi (Patent 6,172,305) to teach the inclusion of a voltage bus bar, and a combination using Review of BGAs (a 1998 conference paper) with Devnani and CRTA (a 1994 reliability report) to teach the fundamental high-stress nature of die corners.

4. Arguments Regarding Discretionary Denial

• Fintiv Factors (§314(a)): Petitioner argued that discretionary denial under Fintiv would be inappropriate. It was contended that the co-pending district court trial was likely to be delayed past the IPR’s Final Written Decision (FWD) date. Further, Petitioner asserted it acted with diligence by filing the petition within six months of receiving infringement contentions. The petition also challenged claims (2-4 and 7-12) not asserted in the district court litigation, arguing that institution would promote system efficiency by providing the only venue for adjudicating the validity of those claims.
• Same or Substantially the Same Prior Art (§325(d)): Petitioner argued that denial under §325(d) was not warranted because the Examiner did not previously consider the asserted combinations of prior art. While Pillai and Tanahashi were cited during prosecution, they were presented in this petition in new combinations with previously unconsidered references (Devnani, Chung, Celeron, AAPA). Petitioner maintained that these new combinations raised different questions of patentability than those considered by the Examiner, particularly since the Examiner never evaluated an obviousness rejection combining the AAPA or Pillai with other references.

5. Relief Requested

• Petitioner requests institution of an inter partes review and cancellation of claims 1-12 of Patent 7,345,245 as unpatentable.