Silicon Motion Inc v. Unification Technologies LLC

1. Case Identification

• Case #: IPR2024-00199
• Patent #: 11,640,359
• Filed: December 18, 2023
• Petitioner(s): Silicon Motion Inc.
• Patent Owner(s): Unification Technologies LLC
• Challenged Claims: 7 and 10-17

2. Patent Overview

• Title: Systems and Methods for Identifying Storage Resources That Are Not In Use
• Brief Description: The ’359 patent discloses methods for managing data in a block-based NAND flash storage system. The method involves a host processor creating an "empty-block identifier" upon file deletion, which is sent to a NAND controller that updates an index of mappings to indicate the associated data no longer needs to be preserved.

3. Grounds for Unpatentability

Ground 1: Claims 7 and 10-17 are obvious over Suda in view of POSITA knowledge.

• Prior Art Relied Upon: Suda (Patent 7,057,942).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Suda taught all limitations of independent claim 7. Suda disclosed a memory device with a controller managing a logical-to-physical address table, which Petitioner equated to the claimed "index of mappings." Petitioner asserted that Suda’s "erase command," which designates a logical address for deletion, constituted the claimed "empty-block identifier." The key limitation of "updating the index ... to indicate that data ... does not need to be preserved" was allegedly met by Suda's process of using "erasure area pointers" to mark data in a "virtual erased state" or, in other cases, by canceling the relation between logical and physical addresses in its table. For dependent claims, Petitioner contended that Suda’s disclosure of garbage collection and overwriting entire blocks satisfied the limitations of claims 10-17.
  • Motivation to Combine (for §103 grounds): This ground relied on a single reference plus the knowledge of a Person of Ordinary Skill in the Art (POSITA). Petitioner argued a POSITA would have understood that a host device, such as Suda's digital camera, contains a host processor and that erase commands are standard operations for managing file deletions in such systems.
  • Expectation of Success (for §103 grounds): A POSITA would have had a high expectation of success in applying general knowledge about host processors and file systems to Suda’s memory management system.

Ground 2: Claims 7 and 10-17 are obvious over Bennett in view of POSITA knowledge.

• Prior Art Relied Upon: Bennett (Patent 7,624,239).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Bennett, which disclosed methods for managing erase operations in non-volatile memory, rendered the claims obvious. Bennett’s "memory-side memory manager" (controller) maintained a "Group Address Table" (GAT), which served as the claimed "index of mappings." Petitioner asserted that an "Erase Sectors command" originating from the host constituted the claimed "empty-block identifier." The "updating the index" limitation was allegedly met by Bennett’s teaching of "logically erasing" data, which involved marking sectors as erased by setting an "erased" flag in the GAT. This flag indicated the data need not be preserved and could be physically erased later during a background garbage collection process.
  • Motivation to Combine (for §103 grounds): This ground relied on Bennett supplemented by POSITA knowledge. Petitioner asserted a POSITA would understand that an erase command from a host system inherently serves as an indication of file deletion and that Bennett's system of using flags was a standard technique for managing data erasure efficiently.
  • Expectation of Success (for §103 grounds): A POSITA would have expected success in implementing Bennett’s logical erasure methods, as they were described as common techniques for advanced memory systems to improve performance by deferring time-consuming physical erasures.

Ground 3: Claim 11 is obvious over Suda and/or Bennett in further view of Zipprich.

• Prior Art Relied Upon: Suda (Patent 7,057,942), Bennett (Patent 7,624,239), and Zipprich (Application # 2003/0079078).

• Core Argument for this Ground:

  • Prior Art Mapping: This ground specifically addressed dependent claim 11, which added the limitation of "transmitting a message indicating that the data ... has been overwritten." Petitioner argued that while Suda and Bennett taught the underlying erasure process, Zipprich explicitly disclosed generating a "status report" to provide feedback and track overwrite events. This report, which could be an email or log file entry, fulfilled the "transmitting a message" limitation.
  • Motivation to Combine (for §103 grounds): A POSITA would combine Zipprich's status reporting with the memory management systems of Suda or Bennett to improve system performance and reliability. Providing confirmation that an erasure is complete would allow a host system to know that physical memory space is available for new data, which is a simple and predictable improvement.
  • Expectation of Success (for §103 grounds): The combination would have been straightforward, as adding a status notification function to an existing data management process was a well-known programming task.

• Additional Grounds: Petitioner asserted additional obviousness challenges, including that claims 7 and 10-13 are obvious over Bennett in view of Suda, and that claims 13-15 are obvious over Suda and/or Bennett in view of SwSTE'05 (a 2005 article on flash memory structures).

4. Arguments Regarding Discretionary Denial

• Petitioner argued that discretionary denial under 35 U.S.C. §325(d) was inappropriate because the primary references, Suda and Bennett, were not substantively considered during prosecution despite being cited in an information disclosure statement. Petitioner highlighted that in a prior inter partes review (IPR) against a related patent (IPR2021-00345), the Board found substantially identical claims unpatentable over Suda, demonstrating Patent Office error.
• Petitioner also stipulated that if the IPR is instituted, it will not pursue in parallel district court proceedings the same grounds or any grounds that could have reasonably been raised in the petition, thereby arguing against discretionary denial under §314(a).

5. Relief Requested

• Petitioner requests institution of an IPR and cancellation of claims 7 and 10-17 of the ’359 patent as unpatentable.