Semiconductor Components Industries LLC v. Greenthread LLC

1. Case Identification

• Case #: IPR2023-00263
• Patent #: 11,316,014
• Filed: December 11, 2023
• Petitioner(s): Semiconductor Components Industries, LLC
• Patent Owner(s): Greenthread LLC
• Challenged Claims: 1-9, 13-28

2. Patent Overview

• Title: Semiconductor Device and System
• Brief Description: The ’014 patent describes an electronic system with a semiconductor device having graded dopant concentrations. The graded doping is configured to create an electric field that aids the movement of charge carriers away from active surface regions and towards a deeper area of the substrate, ostensibly to mitigate soft errors caused by particle strikes.

3. Grounds for Unpatentability

Ground 1: Obviousness over Kawagoe - Claims 1-9 and 13-28 are obvious over Kawagoe.

• Prior Art Relied Upon: Kawagoe (Patent 6,043,114).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner asserted that Kawagoe, a single reference, teaches all limitations of the challenged claims. Kawagoe discloses a twin-well CMOS device fabricated on an epitaxial substrate. It explicitly teaches forming active regions for nMOS and pMOS transistors, separated by isolation regions. Critically, Kawagoe describes forming wells with impurity concentrations that are “gradually lowered in the depthwise direction” away from the surface. Petitioner argued this downward-sloping gradient serves the claimed purpose of aiding carrier movement (specifically, electrons produced by alpha particles) toward the substrate body to reduce soft errors in devices like DRAMs.
  • Motivation to Combine: Not applicable as this is a single-reference ground. However, Petitioner argued a person of ordinary skill in the art (POSITA) would find it obvious to combine features from different embodiments within Kawagoe. Specifically, a POSITA would use the uniformly-doped epitaxial substrate from Kawagoe’s Embodiment 1 (noted for its lower cost and higher quality) with the twin-well CMOS device of Embodiment 4, as this would be a simple and predictable substitution of known elements for known purposes.
  • Expectation of Success: A POSITA would have a high expectation of success because Kawagoe itself describes using both uniformly-doped and latchup-resistant substrates for forming CMOS devices, emphasizing their similar utility and predictable results.

Ground 2: Obviousness over Wieczorek and Wolf - Claims 1-2, 4-9, 13-23, and 25-28 are obvious over Wieczorek in view of Wolf.

• Prior Art Relied Upon: Wieczorek (Application # 2003/0183856) and Wolf (Stanley Wolf and Richard N. Tauber, Silicon Processing for the VLSI Era, 2000).

• Core Argument for this Ground:

  • Prior Art Mapping: Petitioner contended that Wieczorek discloses a conventional twin-well CMOS device with all the core structural elements of the claims, including a first active region (for an N-channel transistor) and a second active region (for a P-channel transistor) formed in respective P-wells and N-wells. Wieczorek’s figures illustrate a dopant profile for the wells that is highest at the surface and decreases with depth, creating the claimed graded dopant concentration. Wolf, a well-known textbook, was introduced to supply the teaching of using a standard, uniformly-doped substrate, which Wieczorek described generally as "an appropriate substrate."
  • Motivation to Combine: A POSITA, when implementing the conventional CMOS process described in Wieczorek, would have been motivated to consult a standard textbook like Wolf for details on selecting a suitable substrate. Wolf confirms that a "uniform, lightly doped p- or n-type substrate" is commonly used for twin-well CMOS devices. This combination represented applying a known technique (substrate selection from Wolf) to a known device (Wieczorek's CMOS) to achieve a predictable result.
  • Expectation of Success: Success would have been expected because the combination merely involved using a standard, well-documented substrate type for a standard, well-documented CMOS fabrication process.

• Additional Grounds: Petitioner asserted additional obviousness challenges based on combining the primary references with Gupta (Patent 6,163,877) to explicitly teach a plurality of transistors in each active region, and with Silverbrook (Patent 6,614,560) to render it obvious to implement the designs in a CMOS image sensor.

4. Key Claim Construction Positions

• Petitioner argued that no claim terms required construction to resolve the issues. However, it noted that its invalidity arguments hold true even under the alternative constructions for terms like “active region” and “well region” that were proposed by the Patent Owner and a third party (Intel) in related district court litigation. Petitioner contended that both Kawagoe and Wieczorek satisfy either the plain meaning or the proposed constructions for these terms.

5. Key Technical Contentions (Beyond Claim Construction)

• A central technical contention was that a downward-sloping graded dopant concentration was well-known in the prior art to create an inherent, "built-in" unidirectional electric field. Petitioner supported this by citing the prosecution history of the ’014 patent’s parent, where the applicant itself argued this principle to the Patent Office. This inherent field, Petitioner asserted, necessarily "sweeps" or "aids" the movement of charge carriers deep into the substrate, directly corresponding to the primary functional limitation of the challenged claims.

6. Arguments Regarding Discretionary Denial

• Petitioner argued against discretionary denial under both 35 U.S.C. §314(a) (Fintiv) and §325(d).
• §314(a) / Fintiv: Petitioner contended that the petition presents compelling evidence of unpatentability, particularly the single-reference obviousness ground based on Kawagoe. It also argued that the parallel litigation is at an early stage with no significant investment of judicial resources, and a stay is likely, weighing against denial.
• §325(d): Petitioner asserted that the primary references (Kawagoe, Wolf, Gupta, Silverbrook) were never cited or discussed by the examiner during prosecution. It argued the new art is not cumulative to the art of record, as the prosecution history involved different claim limitations and relied on a non-prior art reference.

7. Relief Requested

• Petitioner requests institution of inter partes review (IPR) and cancellation of claims 1-9 and 13-28 of the ’014 patent as unpatentable.