Semiconductor Components Industries LLC v. Greenthread LLC

1. Case Identification

• Case #: IPR2023-00266
• Patent #: 8,421,195
• Filed: December 11, 2023
• Petitioner(s): Semiconductor Components Industries, LLC
• Patent Owner(s): Greenthread, LLC
• Challenged Claims: 1-6

2. Patent Overview

• Title: CMOS Semiconductor Device and Method for Making the Same
• Brief Description: The ’195 patent relates to CMOS semiconductor devices featuring graded dopant concentrations in specific regions. The invention claims that these graded concentrations create static, unidirectional electric drift fields that aid the movement of minority carriers away from the device's surface layer and toward the substrate, intended to improve device performance.

3. Grounds for Unpatentability

Ground 1: Obviousness over Payne - Claims 1-2 and 4-6 are obvious over Payne.

• Prior Art Relied Upon: Payne (Patent 4,684,971).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Payne, a single reference, discloses every limitation of the challenged claims. Payne teaches a high-packing-density CMOS device with a nested well structure, comprising shallow "surface regions" (18, 20) formed within deep "tub regions" (15, 17). Petitioner asserted that Payne's deep "tub region" corresponds to the claimed "single drift layer," and the shallow "surface region" disposed within it corresponds to the claimed "well region." Payne further discloses a "high-low implant profile" with a dopant concentration that decreases with depth, which Petitioner argued inherently creates the claimed first and second static unidirectional electric drift fields to aid minority carrier movement, as was well understood in the art and admitted by the patentee during prosecution.
  • Motivation to Combine (for §103 grounds): Not applicable (single reference ground).
  • Expectation of Success (for §103 grounds): Not applicable (single reference ground).
  • Key Aspects: Petitioner contended that dependent claims 4, 5, and 6, which recite linear, quasi-linear, and exponential gradients, are disclosed by the illustrative dopant profile in Payne's Figure 11. They argued these gradients were well-known variations obvious to a person of ordinary skill in the art (POSITA). Claim 2, reciting a "deeply-implanted layer," was argued to be met because Payne's deep tub regions are formed by ion implantation and extend to depths (3-8µm) consistent with this term.

Ground 2: Obviousness over Sakai and Kawagoe - Claims 1-6 are obvious over Sakai in view of Kawagoe.

• Prior Art Relied Upon: Sakai (Patent 4,907,058) and Kawagoe (Patent 6,043,114).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Sakai discloses a nested "twin double well structure" for high-packing-density CMOS memory devices, structurally similar to the device claimed in the ’195 patent. Sakai's deep wells correspond to the claimed "single drift layer," and its shallow wells correspond to the claimed "well region." While Sakai teaches a high-to-low dopant concentration between its shallow and deep wells, Petitioner used Kawagoe to explicitly teach implementing this as a graded, downward-sloping concentration. Kawagoe teaches that such graded profiles create a drift field that sweeps away unwanted minority carriers generated by alpha particles, thereby reducing "soft errors."
  • Motivation to Combine (for §103 grounds): A POSITA would combine Sakai with Kawagoe to improve the reliability of Sakai’s high-density memory devices. High-density devices, like those in Sakai, were known to be susceptible to soft errors. Kawagoe provided a known solution—a graded dopant profile—to address this known problem. Both references are from the same assignee (Hitachi) and directed to similar CMOS technology, enhancing the motivation.
  • Expectation of Success (for §103 grounds): A POSITA would have an expectation of success because implementing graded dopant profiles via ion implantation and thermal diffusion (as taught in the references) was a well-known and predictable process for improving device performance by reducing soft errors.

Ground 3: Obviousness over Payne and Wolf - Claims 2 and 3 are obvious over Payne in view of Wolf.

• Prior Art Relied Upon: Payne (Patent 4,684,971) and Wolf (a 4-volume textbook, Silicon Processing For The VLSI Era).

• Core Argument for this Ground:

  • Prior Art Mapping: This ground builds on Payne by leveraging the well-known teachings of the Wolf textbook to render dependent claims 2 and 3 obvious. For claim 2 ("deeply-implanted layer"), Wolf teaches using high-energy "MeV implantation" to form deep CMOS wells, which buries ion damage far from the sensitive surface region. For claim 3 ("epitaxial layer"), Wolf teaches fabricating twin-tub CMOS devices on an epitaxial substrate to suppress latch-up, a known failure mechanism exacerbated by the high packing density sought by Payne.
  • Motivation to Combine (for §103 grounds): A POSITA would combine Payne with Wolf to implement known, advantageous manufacturing techniques. To form Payne's deep wells while minimizing surface damage, a POSITA would look to Wolf's teachings on high-energy implantation. Similarly, to mitigate the known risk of latch-up in Payne's high-density design, a POSITA would adopt Wolf’s teaching of using an epitaxial layer, which was a standard industry solution.
  • Expectation of Success (for §103 grounds): Success was predictable, as Wolf documents standard, widely used processes for forming deep wells and preventing latch-up in CMOS devices like those disclosed in Payne.

• Additional Grounds: Petitioner asserted additional obviousness challenges, including claim 3 over Payne and Parrillo (Patent 4,435,896), and claim 2 over Sakai, Kawagoe, and Wolf, relying on similar motivations to apply known latch-up prevention and deep implantation techniques.

4. Arguments Regarding Discretionary Denial

• Petitioner argued against discretionary denial under §314(a) (Fintiv), asserting that the petition presents compelling evidence of unpatentability, particularly the single-reference obviousness ground over Payne. Further, the parallel district court litigation trial is not scheduled until September/October 2025, long after a Final Written Decision would issue, and the court has not invested significant resources.
• Petitioner also argued against denial under §325(d), stating that none of the primary prior art references (Payne, Sakai, Kawagoe, Wolf, Parrillo) were cited or considered by the Examiner during the original prosecution of the ’195 patent. Therefore, the arguments and references are not cumulative to those previously before the Patent Office.

5. Relief Requested

• Petitioner requests institution of inter partes review and cancellation of claims 1-6 of the ’195 patent as unpatentable under 35 U.S.C. §103.