Monolithic Power Systems Inc v. Greenthread LLC

1. Case Identification

• Case #: IPR2024-00468
• Patent #: 8,421,195
• Filed: February 2, 2024
• Petitioner(s): Monolithic Power Systems, Inc.
• Patent Owner(s): Greenthread LLC
• Challenged Claims: 1-3, 5, and 6

2. Patent Overview

• Title: CMOS Semiconductor Device with Graded Dopant Concentration
• Brief Description: The ’195 patent relates to a Complementary Metal-Oxide-Semiconductor (CMOS) device featuring semiconductor layers with a graded dopant concentration. This gradient is designed to create a static electric drift field that sweeps minority carriers away from the active surface region and towards the substrate, purportedly to improve device performance by mitigating the effects of unwanted carriers.

3. Grounds for Unpatentability

Ground I: Obviousness over Onoda - Claims 1-3, 5, and 6 are obvious over Onoda.

• Prior Art Relied Upon: Onoda (Japanese Application H8-279598).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Onoda teaches all elements of the challenged claims. Onoda’s flash memory device includes both N-channel MOS (NMOS) and P-channel MOS (PMOS) transistors; Petitioner contended a POSITA would understand this to disclose a CMOS device, as CMOS was the dominant fabrication technology for memory devices at the time. Petitioner mapped Onoda’s structure to claim 1 by identifying a surface layer containing an active region, an underlying substrate (101), and a single drift layer (epitaxial layer 102) between them. This drift layer and the well regions within it (e.g., 105a) possess a graded dopant concentration that decreases with depth, as shown in Onoda’s dopant profile graphs. Petitioner asserted this downward gradient inherently creates the claimed "first static unidirectional electric drift field" to sweep minority carriers toward the substrate. The well region (105a) itself has a graded profile, creating the "second" such field. For dependent claims, Petitioner argued Onoda’s drift layer is "deeply-implanted" (extending ~5µm deep), is an "epitaxial layer," and its dopant profiles, described as approximating Gaussian distributions, would be understood by a POSITA to teach or render obvious both "quasi-linear" and "exponential" gradients.
  • Key Aspects: Petitioner’s argument centered on the contention that creating a static, unidirectional electric drift field is an inherent and well-understood property of a downward-sloping dopant gradient. This principle was allegedly so well-known that the Patent Owner acknowledged it during prosecution of a related patent.

Ground II: Obviousness over Onoda and Nishizawa - Claims 1-3, 5, and 6 are obvious over Onoda in view of Nishizawa.

• Prior Art Relied Upon: Onoda (Japanese Application H8-279598) and Nishizawa (Patent 5,384,476).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground reinforces the challenge by using Nishizawa to make explicit what Petitioner claims is inherent in Onoda. Nishizawa explicitly discloses using a graded "impurity concentration gradient" to create a "drift electric field" for the express purpose of drifting minority carriers to the substrate to prevent device errors. Petitioner argued this provides an explicit rationale for the function of the structure found in Onoda, removing any potential ambiguity about the purpose of Onoda’s graded dopant profile.
  • Motivation to Combine: A POSITA would combine Onoda’s device structure with Nishizawa’s explicit functional teachings. Both references address semiconductor memory devices and related problems like punch-through. A POSITA would find it obvious to apply the explicit field-creation principles described in Nishizawa to the analogous graded-dopant structure in Onoda to improve device reliability, a predictable outcome and known goal in the art.
  • Expectation of Success: The combination involved applying an express principle from Nishizawa to a suitable, known structure in Onoda. Because this combined known elements to achieve a predictable improvement, a POSITA would have had a reasonable expectation of success.

Ground III: Obviousness over Kawagoe - Claims 1-3, 5, and 6 are obvious over Kawagoe.

• Prior Art Relied Upon: Kawagoe (Patent 6,043,114).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner asserted that Kawagoe alone renders the claims obvious by teaching a CMOS device with an epitaxial layer whose impurity concentration is graded downward to attract minority carriers to the substrate. This structure and purpose directly match the ’195 patent’s objective. Petitioner mapped Kawagoe's epitaxial layer (2E) and part of its substrate body (2S) to the "single drift layer." This layer contains p- and n-wells, has a graded dopant profile creating the claimed static drift field, and the wells within it also have graded profiles creating the second claimed field. Petitioner also addressed the dependent claims by arguing Kawagoe’s diffusion layer is "deeply-implanted" because it extends into the substrate; is an "epitaxial layer" as it is formed in an epitaxial wafer; and its graphical depiction of dopant profiles (FIG. 17) would be understood to encompass quasi-linear and exponential gradients.
  • Key Aspects: A central contention was that a POSITA would equate Kawagoe’s “diffusion layer” with the claimed “drift layer.” Petitioner argued the terms describe the same physical structure—a region with a graded dopant profile created by impurity diffusion to control carrier movement. Further, Petitioner argued that even if the well regions in Kawagoe are not entirely contained within the drift layer, the claim language “disposed in” does not require complete containment, making Kawagoe’s structure relevant.

4. Arguments Regarding Discretionary Denial

• Petitioner argued against discretionary denial under 35 U.S.C. §314(a) and the Fintiv factors, contending it presented "compelling evidence of unpatentability." It emphasized that none of the primary references (Onoda, Kawagoe, Nishizawa) were examined during the original prosecution.
• Petitioner also argued against denial under 35 U.S.C. §325(d), asserting that the grounds are not cumulative to art considered by the examiner. It stated that the new references teach relevant CMOS memory device structures with graded dopants in a manner that the previously considered art (Rhodes) did not, an issue the Patent Owner itself successfully argued during prosecution to overcome prior rejections.

5. Relief Requested

• Petitioner requests institution of an inter partes review and cancellation of claims 1-3, 5, and 6 of the ’195 patent as unpatentable under 35 U.S.C. §103.