PTAB

IPR2024-00553

Monolithic Power Systems Inc v. Greenthread LLC

Key Events

Petition

petition

Title: Semiconductor Device with Graded Doping Profile
Brief Description: The ’014 patent discloses a semiconductor device with graded dopant concentrations in its layers. This gradient is designed to create a static drift field that sweeps minority carriers away from the device's surface active regions and toward the substrate, purportedly to improve device performance and reliability.

Prior Art Relied Upon: Kawagoe (Patent 6,043,114).
Core Argument for this Ground:
- Prior Art Mapping: Petitioner argued that Kawagoe teaches a semiconductor device for memory applications that discloses all limitations of the challenged claims. Specifically, Kawagoe describes a p-type substrate with an epitaxial layer, n-well and p-well active regions for forming CMOS transistors, and an "impurity concentration gradually lowered depthwise." This graded dopant concentration is explicitly taught to create a gradient that attracts minority carriers (electrons) toward the substrate body to reduce soft errors caused by alpha particles. This structure and function allegedly meet the limitations of independent claims 1 and 21, including the substrate, separate active regions, transistors, and a graded dopant region to aid carrier movement toward an area with no active regions.
- Key Aspects: Petitioner contended that Kawagoe's teaching of using a downward-sloping dopant profile to mitigate soft errors by sweeping minority carriers to the substrate is the same fundamental concept claimed in the ’014 patent. For claim 21's requirement of a "linear, quasilinear..." profile, Petitioner argued that Kawagoe's depicted profile is quasi-linear and, in any case, selecting a specific known profile shape would have been an obvious design choice for a POSITA.

Prior Art Relied Upon: Onoda (Japanese Application H8-279598).
Core Argument for this Ground:
- Prior Art Mapping: Petitioner asserted that Onoda, a reference not considered during prosecution, discloses a nonvolatile semiconductor storage device that renders the claims obvious. Onoda teaches a p-type substrate comprising a heavily-doped layer and a lightly-doped epitaxial layer on top. Within this structure, Onoda forms multiple p-wells and n-wells containing NMOS and PMOS transistors, respectively. Critically, Onoda discloses that these well regions have a graded dopant profile, with concentration decreasing as a function of depth, to improve latch-up resistance. Petitioner argued this downward gradient inherently aids the movement of minority carriers from the surface active regions toward the substrate, thus teaching the core invention.
- Key Aspects: Onoda's disclosure of graded p-wells and n-wells, each with a dopant concentration decreasing with depth, was presented as directly teaching the limitations of claims 1 and 21. Petitioner argued a POSITA would have understood that this known technique of graded doping to control carrier movement in a flash memory device would be directly applicable and beneficial for any logic device facing similar minority carrier issues.

Prior Art Relied Upon: Onoda (Japanese Application H8-279598) and Nishizawa (Patent 5,384,476).
Core Argument for this Ground:
- Prior Art Mapping: Onoda was argued to provide the base semiconductor structure, including a substrate with multiple active regions in wells whose dopant concentrations have a downward gradient. Nishizawa was argued to explicitly teach the purpose and benefit of such a structure. Nishizawa discloses a DRAM device with a buried region having a graded dopant profile ("progressively decreasing toward the p type substrate") that is deliberately created to establish a drift electric field. This field functions to sweep minority carriers away from the surface circuitry and into the substrate to prevent memory errors.
- Motivation to Combine: A POSITA would combine these references because both address the same problem of controlling unwanted minority carrier movement in semiconductor devices using a graded doping profile. Petitioner argued a POSITA would look to Nishizawa’s explicit teachings on using a drift field created by a graded dopant profile to solve the latch-up issues described in Onoda, as latch-up is a well-known problem related to minority carrier injection.
- Expectation of Success: The combination would yield predictable results because it involves applying Nishizawa's well-understood principle of using a graded profile to create a carrier-sweeping drift field to Onoda's similar semiconductor structure.

Petitioner argued that the Board should not exercise its discretion to deny institution under §314(a) or §325(d).
Under §314(a) (Fintiv), Petitioner asserted it presented compelling evidence of unpatentability, particularly through the Onoda and Nishizawa references, which were never considered by the USPTO.
Under §325(d), Petitioner contended that the asserted prior art is not cumulative to the art examined during prosecution. It argued that Onoda and Kawagoe describe CMOS memory devices with graded dopants in active wells, a context different from the image sensor technology in the primary reference (Rhodes) overcome during prosecution.
Regarding prior petitions by other parties (General Plastic factors), Petitioner asserted it is a separate entity with no significant relationship to other petitioners, this is its first petition against the ’014 patent, and it presents new grounds and evidence not found in other pending IPRs.

Petitioner requested institution of an inter partes review and cancellation of claims 1, 3-9, 13, 15-17, 20-21, and 23-28 of the ’014 patent as unpatentable.