Texas Instruments Inc v. Greenthread LLC

1. Case Identification

• Case #: IPR2024-00673
• Patent #: 11,121,222
• Filed: March 12, 2024
• Petitioner(s): Texas Instruments Incorporated
• Patent Owner(s): Greenthread LLC
• Challenged Claims: 1-9, 13-28, 32-42

2. Patent Overview

• Title: VLSI Semiconductor Device
• Brief Description: The ’222 patent describes a very-large-scale integration (VLSI) semiconductor device designed to mitigate radiation-induced soft errors. The invention focuses on creating a graded dopant concentration profile within active regions and adjacent well regions to establish a built-in electric field that directs charge carriers away from sensitive device areas and deep into the substrate.

3. Grounds for Unpatentability

Ground I: Claims 1-9, 13-14, 16-21, and 23-42 are obvious over Kawagoe.

• Prior Art Relied Upon: Kawagoe (Patent 6,043,114).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Kawagoe, which teaches a semiconductor integrated circuit device, discloses every limitation of the challenged claims. Kawagoe describes a twin-well CMOS device built on a p-type epitaxial substrate, containing separate active regions for nMOS and pMOS transistors. Critically, Petitioner asserted that Kawagoe explicitly teaches fabricating well regions with impurity concentrations that are "gradually lowered in the depthwise direction" from the surface. This downward-sloping graded dopant concentration was argued to meet the central claim limitation of aiding carrier movement from the surface towards the substrate to reduce soft errors in devices like DRAMs.
  • Motivation to Combine (for §103 grounds): This ground is based on a single reference. Petitioner argued a person of ordinary skill in the art (POSITA) would be motivated to select a uniformly-doped epitaxial substrate, which is one of the options described in Kawagoe, to achieve benefits of lower cost and excellent film quality, while still satisfying the claim limitations.
  • Expectation of Success (for §103 grounds): A POSITA would have had a high expectation of success because Kawagoe details the structure and benefits of using graded dopant wells to mitigate soft errors in CMOS devices, directly aligning with the purpose of the challenged patent.

Ground II: Claims 1-2, 4-9, 13-23, 25-28, and 32-42 are obvious over Wieczorek in view of Wolf.

• Prior Art Relied Upon: Wieczorek (Application # 2003/0183856) and Wolf (Silicon Processing for the VLSI Era, 2000).

• Core Argument for this Ground:

  • Prior Art Mapping: Petitioner contended that Wieczorek discloses a conventional twin-well CMOS device with all the core structural elements of the claims, including separate active regions, transistors, and well regions. The petition argued that the typical dopant profiles shown in Wieczorek, which depict concentration decreasing with depth after heat treatments, inherently teach the claimed graded dopant concentration. Wolf, a standard textbook on VLSI processing, was cited to supply details that would have been common knowledge for a conventional device, such as the use of a uniform, lightly doped p-type or n-type substrate.
  • Motivation to Combine (for §103 grounds): A POSITA, when implementing the conventional CMOS device described in Wieczorek, would naturally consult a standard, authoritative textbook like Wolf for foundational details, such as selecting an appropriate starting substrate. The combination was framed as applying routine, well-understood principles from Wolf to the conventional device layout in Wieczorek.
  • Expectation of Success (for §103 grounds): A POSITA would have a reasonable expectation of success because the combination involves nothing more than fabricating a conventional CMOS device using standard materials and processes well-documented in the art, leading to a predictable outcome.

• Additional Grounds: Petitioner asserted additional obviousness challenges based on:

  • Kawagoe in view of Gupta (Patent 6,163,877)
  • Wieczorek and Wolf in view of Gupta
  • Kawagoe in view of Silverbrook (Patent 6,614,560)
  • Wieczorek and Wolf in view of Silverbrook

• These grounds relied on similar theories, adding Gupta to address claims requiring a plurality of transistors by teaching high-density layout techniques, and adding Silverbrook to explicitly teach the implementation of the CMOS designs in an image sensor.

4. Arguments Regarding Discretionary Denial

• Petitioner argued that discretionary denial under the Fintiv factors would be inappropriate. The petition asserted that the Final Written Decision (FWD) for the co-pending IPR proceeding it seeks to join is anticipated on February 12, 2025, while the parallel district court trial is not scheduled to begin until March 3, 2025. This timeline suggests the Board will resolve validity issues before the trial, promoting efficiency and simplifying issues for the district court.
• The petition also argued against denial under 35 U.S.C. §325(d), emphasizing that the primary prior art references relied upon—Kawagoe, Wolf, Gupta, and Silverbrook—were not cited or substantively considered by the Examiner during the original prosecution of the ’222 patent.

5. Relief Requested

• Petitioner requests institution of an inter partes review (IPR) and cancellation of claims 1-9, 13-28, and 32-42 of the ’222 patent as unpatentable.