Texas Instruments Inc v. Greenthread LLC

1. Case Identification

• Case #: IPR2024-00771
• Patent #: 8,421,195
• Filed: April 10, 2024
• Petitioner(s): Texas Instruments Incorporated
• Patent Owner(s): Greenthread LLC
• Challenged Claims: 1-6

2. Patent Overview

• Title: CMOS Semiconductor Device
• Brief Description: The ’195 patent is directed to a Complementary Metal-Oxide Semiconductor (CMOS) device with graded dopant concentrations designed to aid the movement of minority charge carriers away from the surface active regions and into the substrate, thereby improving device performance and reliability.

3. Grounds for Unpatentability

Ground 1: Claims 1-2 and 4-6 are obvious over Payne

• Prior Art Relied Upon: Payne (Patent 4,684,971).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Payne, which teaches an ion-implanted CMOS device, discloses every limitation of the challenged claims. Payne’s nested well structure, comprising deep "tub regions" (e.g., region 15) containing shallower "surface regions" (e.g., region 18), was mapped to the claimed "single drift layer" containing a "well region." The active source/drain regions are formed within this surface region. Payne’s Figure 11 illustrates a "high-low implant profile" which creates a downward-sloping graded dopant concentration through the nested wells. Petitioner asserted that, based on the patent owner's own prosecution arguments regarding similar profiles, this graded concentration inherently creates the claimed static, unidirectional electric drift fields that aid the movement of minority carriers from the surface layer toward the substrate. Dependent claim 2’s “deeply-implanted layer” was met by Payne’s deep tub regions (3-8µm deep), and claims 4-6 were met because Payne’s dopant profile includes regions with linear/quasi-linear and exponential gradients.
  • Key Aspects: The argument relied heavily on admissions made by the patent owner during the original prosecution of the ’195 patent, applying them to the nearly identical dopant profiles disclosed in Payne to establish the presence and function of the claimed electric fields.

Ground 2: Claims 1-6 are anticipated by Onoda or obvious over Onoda in view of Wolf

• Prior Art Relied Upon: Onoda (Japanese Application H8-279598) and Wolf (Silicon Processing For The VLSI Era, 2000).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner asserted Onoda anticipates claims 1-6. Onoda discloses a flash memory device built on a semiconductor structure with a heavily-doped P-type substrate (layer 101) and a lightly-doped P-type second semiconductor layer (layer 102) formed on top via epitaxial deposition. This layer 102 was identified as the claimed "single drift layer." Within this drift layer, Onoda forms various P-wells and N-wells (e.g., 105a) that function as the claimed "well region." Onoda’s Figure 11 explicitly shows a downward-sloping, graded dopant concentration profile extending from the surface through the well region and drift layer to the substrate. This graded profile, formed by ion implantation and thermal diffusion, was argued to create the claimed static electric drift fields. Onoda's drift layer is formed via implantation to a depth of about 5 µm, meeting the "deeply-implanted" limitation, and is also explicitly described as an "epitaxial layer," meeting claim 3. Petitioner’s analysis showed Onoda’s dopant profile also contains linear and exponential segments.
  • Motivation to Combine (for §103 grounds): To the extent Onoda was deemed not to explicitly disclose a CMOS device, Petitioner argued a POSITA would combine Onoda with the teachings of Wolf, a well-known textbook. The motivation would be to implement the known low-power benefits of CMOS technology (taught by Wolf) into Onoda's flash memory device, which already contained both NMOS and PMOS transistors suitable for a CMOS implementation. A POSITA would also combine them to use Wolf’s advanced high-energy ion implantation techniques to form Onoda’s deep wells, thereby minimizing damage to critical surface structures.
  • Expectation of Success: A POSITA would have a high expectation of success, as the combination involved applying standard, well-understood CMOS principles and fabrication techniques described in Wolf to improve the predictable performance characteristics (power consumption, reliability) of a device like Onoda's.

Ground 3: Claims 2 and 3 are obvious over Payne in view of Wolf

• Prior Art Relied Upon: Payne (Patent 4,684,971) and Wolf (Silicon Processing For The VLSI Era, 2000).

• Core Argument for this Ground:

  • Prior Art Mapping: This ground specifically addressed the dependent claims for a "deeply-implanted layer" (claim 2) and an "epitaxial layer" (claim 3). While Payne teaches forming deep "tub regions" via ion implantation, Wolf teaches more advanced high-energy ("MeV") implantation to form deep CMOS wells (~1-2 µm or deeper) while advantageously burying most ion damage far below the surface. To improve Payne's device, a POSITA would use Wolf's superior implantation technique. Regarding claim 3, Payne’s high-packing-density design was known to be susceptible to latch-up. Wolf explicitly teaches that fabricating CMOS devices on an epitaxial substrate is a well-known technique to suppress latch-up.
  • Motivation to Combine: A POSITA would combine Payne and Wolf as a simple substitution of a known, improved technique for an older one to gain predictable benefits. Specifically, a POSITA would use Wolf’s high-energy implantation to better form Payne’s deep wells and use Wolf's teaching of epitaxial substrates to solve the known latch-up problem in Payne’s high-density device.
  • Expectation of Success: Success would be expected because both proposed modifications involved applying well-known solutions (high-energy implantation, epitaxial substrates for latch-up) taught in a standard textbook (Wolf) to address known issues or process limitations in a conventional CMOS structure (Payne).

• Additional Grounds: Petitioner asserted an additional obviousness challenge against claim 3 based on Payne in combination with Parrillo (Patent 4,435,896), arguing a POSITA would have been motivated to use the epitaxial substrate taught in the contemporaneous Parrillo patent to mitigate latch-up risk in Payne's device.

4. Arguments Regarding Discretionary Denial

• Petitioner argued against discretionary denial under §314(a) by stating it had provided the Patent Owner a Sotera stipulation not to pursue the same grounds in parallel district court litigation, thereby eliminating concerns of duplicative efforts under the Fintiv framework.
• Petitioner contended that denial under §325(d) was improper because the primary prior art references (Payne, Onoda, Wolf, Parrillo) were never considered during the original prosecution. It further argued the art was not cumulative to the cited reference Rhodes, because Payne and Onoda teach a "nested-well structure" that is functionally and structurally distinct from the side-by-side well architecture taught in Rhodes, a distinction central to the patentable invention.

5. Relief Requested

• Petitioner requests institution of inter partes review and cancellation of claims 1-6 of the ’195 patent as unpatentable.