Micron Technology Inc v. Yangtze Memory Technologies Co Ltd

1. Case Identification

• Case #: IPR2024-00789
• Patent #: 10,861,872
• Filed: April 18, 2024
• Petitioner(s): Micron Technology, Inc.
• Patent Owner(s): Yangtze Memory Technologies Company, Ltd.
• Challenged Claims: 1-6 and 11-13

2. Patent Overview

• Title: Three-Dimensional Memory Device and Method for Forming the Same
• Brief Description: The ’872 patent relates to the fabrication of three-dimensional (3D) NAND memory devices. The technology addresses alleged drawbacks in the "gate-line replacement process" by replacing prior art gate line slits with a plurality of "dummy source structures" that extend vertically through a staircase structure and surround a staircase contact.

3. Grounds for Unpatentability

Ground 1: Claims 1-6, 11, and 13 are obvious over Park.

• Prior Art Relied Upon: Park (Patent 9,859,297).
• Core Argument for this Ground: Petitioner argued that Park, a single prior art reference, teaches every element of the challenged claims, rendering them obvious under 35 U.S.C. §103. The challenge was framed under Petitioner’s proposed construction of "dummy source structure," which requires the structure to occupy a void used for gate replacement.
  • Prior Art Mapping: Petitioner contended that Park’s disclosed "common source lines 144" and "dummy source lines 146" are structurally and functionally equivalent to the ’872 patent’s "dummy source structures." Park allegedly teaches that these lines are formed within openings (voids) that are used for the gate replacement process, a key aspect of Petitioner's proposed claim construction. Petitioner further mapped that Park’s source lines extend vertically through a stepped staircase region and "surround" the staircase contacts (contact plugs 150), consistent with the claims. Crucially, Petitioner asserted that Park’s disclosure of its dummy and common source lines including the "same conductive material" satisfies the "conductive contact" limitation, which was the dispositive feature added during prosecution to secure the allowance of the ’872 patent.

Ground 2: Claims 1-6 and 11-13 are obvious over Tessariol.

• Prior Art Relied Upon: Tessariol (Application # 2019/0081061).
• Core Argument for this Ground: This ground was presented as an alternative invalidity theory, predicated on the Patent Owner’s apparent broader construction of "dummy source structure" which does not require the structure to be formed in a void used for gate-line replacement.
  • Prior Art Mapping: Petitioner argued that Tessariol’s "dummy structures 60" and "operative conductive vias 58," which serve as support pillars, meet the limitations of the challenged claims under this broader interpretation. Tessariol’s structures extend vertically through the memory stack in the staircase region and are arranged to surround staircase contacts. Petitioner emphasized that Tessariol discloses these structures as comprising an "insulative lining 62" and a "conductive core 64 (e.g., metal material)," which directly teaches the "conductive contact" limitation.
  • Motivation to Combine: Although a single-reference ground, the petition argued it would have been obvious for a person of ordinary skill in the art (POSITA) to ensure Tessariol’s dummy structures could contact an upper-level interconnect, if desired. A POSITA would be motivated to form the dummy structures and the operative conductive vias using the same process, as Tessariol teaches, to reduce processing time and cost.
  • Expectation of Success: A POSITA would have had a high expectation of success in implementing this known design choice, as concurrently fabricating different vertical structures with identical material stacks was a common and predictable practice in semiconductor manufacturing.

4. Key Claim Construction Positions

• “dummy source structure”: Petitioner argued this term should be construed as "a structure that occupies the void that was used for the gate replacement process." This proposed construction was presented as central to the invention, aligning with the ’872 patent’s stated purpose of replacing prior art "gate line slits" to solve specific fabrication problems. This construction underpins the primary invalidity ground over Park.
• “surrounding”: Petitioner contended this term does not require complete, continuous encirclement of the staircase contact. This position was based on embodiments within the ’872 patent specification where dummy source structures are depicted with significant gaps between them while still described as "surrounding" a contact. This construction is critical for demonstrating that the arrangements in both Park and Tessariol meet the limitation.

5. Arguments Regarding Discretionary Denial

• Petitioner argued that discretionary denial of institution under 35 U.S.C. §314(a) based on Fintiv factors would be inappropriate. A parallel district court litigation exists, but its scheduled trial date of December 1, 2025, is well after the statutory deadline for a Final Written Decision in the inter partes review (IPR). Petitioner also asserted that minimal investment has occurred in the court proceeding and stipulated that it will not advance the same invalidity grounds in district court, thereby eliminating any significant issue overlap.
• Denial under 35 U.S.C. §325(d) was also argued to be inappropriate. Petitioner asserted that the primary prior art references, Park and Tessariol, were not cited or considered by the Examiner during the original prosecution. The Examiner's allowance was based on the Applicant's amendment adding the "conductive contact" limitation, a feature that Petitioner argued is clearly taught by both asserted references.

6. Relief Requested

• Petitioner requests institution of an IPR and cancellation of claims 1-6 and 11-13 of Patent 10,861,872 as unpatentable.