PTAB

IPR2024-00911

Micron Technology Inc v. Yangtze Memory Technologies Co Ltd

Key Events

Petition

petition

Title: Through Array Contact (TAC) for Three-Dimensional Memory Devices
Brief Description: The 10,937,806 patent describes a three-dimensional (3D) NAND memory device featuring vertical electrical interconnects known as through array contacts (TACs). These TACs extend through the memory array to provide a connection between memory cells and peripheral circuitry.

Prior Art Relied Upon: Toyama (Application # 2017/0179026).
Core Argument for this Ground:
- Prior Art Mapping: Petitioner argued that Toyama’s “Second Modification” embodiment discloses or renders obvious all limitations of independent claim 8, upon which challenged claim 10 depends. Specifically, Petitioner mapped Toyama’s “through-memory-level via region 600” to the claimed TAC region, its “memory array region 100” to the first and second channel regions, and its “dummy memory stack structures 55D” to the non-electrically functional channel structures. For the additional limitations of claim 10, Petitioner asserted Toyama discloses a “substrate” (planar semiconductor material layer 10), an “epitaxial layer” (pedestal channel portions 11), and an “etch stop plug” (drain regions 63, which prevent over-etching during the formation of local contacts).
- Motivation to Combine: For certain elements not explicitly detailed in the cross-sectional views of the Second Modification (e.g., local contacts on slit structures), Petitioner argued a POSITA would have understood their necessity for a functional device and would have been motivated to include them.
- Expectation of Success: A POSITA would have had a high expectation of success in implementing any missing functional elements, as Toyama’s other disclosed embodiments provided clear instructions for their structure and formation.

Prior Art Relied Upon: Toyama (Application # 2017/0179026).
Core Argument for this Ground:
- Prior Art Mapping: Petitioner argued that a POSITA would find it obvious to modify Toyama’s first exemplary structure—which depicts a single memory "plane"—to include multiple planes. This modification, achieved by repeating the single-plane layout side-by-side, inherently creates the claimed “first and second channel regions” with a “TAC region” formed between them. The remaining limitations of claims 8 and 10 were argued to be present in Toyama's base structure.
- Motivation to Combine: A POSITA would combine the teaching of Toyama’s single-plane structure with the well-known concept of a multi-plane architecture to achieve significant, known performance benefits, such as increased read/write throughput and parallelism.
- Expectation of Success: Implementing multiple planes was a common, straightforward, and predictable design choice in the field of NAND flash memory well before the ’806 patent's priority date, ensuring a high expectation of success.

Prior Art Relied Upon: Toyama (Application # 2017/0179026).
Core Argument for this Ground:
- Prior Art Mapping: Petitioner argued for modifying Toyama’s Second Modification by substituting its method of insulating the TACs—using “insulating liners”—with the method taught in Toyama’s First Exemplary Structure, which uses a “unitary dielectric fill material.” This amounts to a simple substitution of one known insulating element for another functionally equivalent element from the same prior art reference.
- Motivation to Combine: A POSITA would be motivated to make this substitution to achieve the necessary electrical isolation of the TACs, a fundamental requirement. Petitioner further contended that using a unitary fill material could provide benefits over the liner-based approach, such as reduced capacitive coupling (crosstalk) between the TACs and adjacent conductive layers.
- Expectation of Success: A POSITA would have had a high expectation of success, as Toyama’s specification explicitly suggests that its various disclosed structures and modifications are compatible and can be combined. The manufacturing processes for both insulating approaches were well-known and compatible.

Petitioner argued that discretionary denial would be inappropriate under both 35 U.S.C. §314(a) and §325(d).
Fintiv Factors (§314(a)): Petitioner argued against denial under Fintiv, stating that the parallel district court trial is scheduled for December 2025, allowing ample time for a Final Written Decision to issue first. Further, Petitioner stipulated it would not advance the IPR grounds in the district court case, thereby eliminating any significant overlap of issues.
Same or Substantially the Same Prior Art (§325(d)): Petitioner contended that denial under §325(d) is unwarranted because the record shows the Examiner did not substantively consider the Toyama reference during prosecution. Petitioner asserted that Patent Owner submitted Toyama as one of 22 references in an Information Disclosure Statement without explaining its high materiality. Crucially, Petitioner argued that Patent Owner failed to disclose to the USPTO that the corresponding Chinese patent application had been rejected over this same Toyama reference, in a rejection that specifically identified how Toyama taught the key limitations of challenged claim 10.

Petitioner requests institution of an inter partes review and cancellation of claim 10 of the ’806 patent as unpatentable.