Texas Instruments Inc v. Bell Semiconductor LLC

1. Case Identification

• Case #: IPR2024-01010
• Patent #: 7,345,245
• Filed: June 7, 2024
• Petitioner(s): Texas Instruments Incorporated
• Patent Owner(s): Bell Semiconductor, LLC
• Challenged Claims: 1-12

2. Patent Overview

• Title: Robust High Density Substrate Design For Thermal Cycling Reliability
• Brief Description: The ’245 patent discloses a semiconductor package design intended to improve reliability during thermal cycling. The invention purports to achieve this by routing signal traces on a bottom routing layer away from a defined “high stress area” that extends approximately two ball pad pitches away from the corner of the integrated circuit die.

3. Grounds for Unpatentability

Ground 1: Obviousness over Devnani and AAPA - Claims 1-2 and 4-5 are obvious over Devnani in view of Applicant's Admitted Prior Art (AAPA).

• Prior Art Relied Upon: Devnani (Application # 2003/0183919) and AAPA (admissions from the ’245 patent prosecution history).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Devnani discloses all basic elements of a multi-layer semiconductor package as required by independent claim 1, including a top layer with a mounted die, a plurality of layers underneath, a bottom routing layer with signal traces, and a ball pad layer. Petitioner asserted that the final limitation—keeping signal traces out of an area within two ball pad pitches of the die corner—is rendered obvious by AAPA. AAPA, as described in the ’245 patent itself, taught the known problem of trace cracking near the high-stress die corner and the existing solution of routing traces outside a defined circular keep-out zone (1 mm radius) to improve reliability.
  • Motivation to Combine: A POSITA would combine Devnani’s standard package structure with the known stress-reduction technique from AAPA for the predictable purpose of preventing trace cracks. Petitioner contended that modifying the size and shape of the AAPA keep-out zone to a two-ball-pad-pitch area is merely an obvious design choice, as the ’245 patent provides no unexpected results for this specific dimension. A POSITA would have been motivated to enlarge the keep-out zone to further reduce the risk of cracking.
  • Expectation of Success: A POSITA would have had a high expectation of success because they would be applying a known technique (routing traces away from a stress area) to a conventional semiconductor package to achieve a known and predictable result (improved reliability).

Ground 2: Obviousness over Chung and Celeron - Claims 1, 2, and 5 are obvious over Chung in view of Celeron.

• Prior Art Relied Upon: Chung (Application # 2003/0003705) and Celeron (a Mobile Intel® Celeron® Processor Datasheet, Apr. 2003).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Chung discloses a semiconductor package with the multi-layer structure recited in claim 1, including a die mounted on a top layer, multiple underlying layers, a bottom routing layer, and a ball pad layer. However, Chung does not explicitly teach routing traces away from an area defined by two ball pad pitches from the die corner. Petitioner contended Celeron remedies this deficiency. The Celeron datasheet explicitly discloses a package with a "clear area" or "package keepout" zone on the bottom of the package that is devoid of ball pads. Based on the dimensions provided in Celeron, Petitioner calculated that this clear area extends more than two ball pad pitches (3.10 mm) from the corner of the die.
  • Motivation to Combine: A POSITA designing a package like Chung’s would have looked to commercial datasheets like Celeron for standard design practices. A POSITA would combine Celeron’s clear area concept with Chung's package to prevent damage to signal traces during thermal cycling, a well-understood problem. This combination would inherently result in a package where no signal traces are located over ball pads within two ball pad pitches of the die corner, as Celeron teaches removing the ball pads themselves from this area.
  • Expectation of Success: The combination was argued to be a straightforward implementation of a known design feature (a keep-out zone) from a commercial product into a similar package structure to solve a known problem, leading to a high expectation of success.

Ground 3: Obviousness over Devnani, AAPA, and Pillai - Claim 3 is obvious over Devnani in view of AAPA, and further in view of Pillai.

• Prior Art Relied Upon: Devnani (Application # 2003/0183919), AAPA, and Pillai (Patent 6,680,530).

• Core Argument for this Ground:

  • Prior Art Mapping: This ground builds on the combination of Devnani and AAPA (as detailed in Ground 1) to meet the limitations of independent claim 1. It adds Pillai to teach the additional limitation of dependent claim 3: a ball pad layer with "no metal traces on the ball pad layer which are connected to the ball pads." Petitioner asserted that Pillai explicitly discloses a ball pad layer where connections are made using vias that pass through the layer, rather than using surface traces on the ball pad layer itself.
  • Motivation to Combine: A POSITA, having already combined Devnani and AAPA, would be motivated to incorporate Pillai's via-based connection scheme. Using vias instead of surface traces on the final layer was a widespread and well-known technique in IC packaging to improve routing efficiency and reduce potential damage to traces during thermal cycling.
  • Expectation of Success: A POSITA would have reasonably expected success in implementing this feature, as it involved substituting one known interconnection method (surface traces) with another (vias) for its known benefits.

• Additional Grounds: Petitioner asserted numerous other obviousness challenges, including combinations of Devnani/AAPA or Chung/Celeron with Tanahashi (Patent 6,172,305) to teach a voltage bus bar on the bottom routing layer (claims 6 and 12). Another ground combined a general review of Ball Grid Arrays (BGAs) with Devnani and CRTA (a 1994 reliability analysis report) to teach routing traces away from high-stress die corners.

4. Arguments Regarding Discretionary Denial

• §325(d) - Same or Substantially the Same Art: Petitioner argued against discretionary denial under §325(d), acknowledging that Pillai and Tanahashi were considered during the original prosecution. However, Petitioner contended they are presented here in a new light. Pillai was previously used in an anticipation rejection, whereas the petition uses it as a secondary reference in novel combinations with Devnani, Chung, and Celeron, none of which were before the Examiner. Similarly, Tanahashi is used in new combinations not previously considered.
• §314(a) - Fintiv Factors: Petitioner argued against discretionary denial under §314(a), stating it has eliminated the risk of duplicative efforts with parallel district court litigation by presenting the Patent Owner with a Sotera stipulation. This stipulation agrees not to pursue the same grounds, or any grounds that could have reasonably been raised in the IPR, in the parallel proceeding, thereby mitigating the concerns underlying the Fintiv factors.

5. Relief Requested

• Petitioner requests institution of an inter partes review and cancellation of claims 1-12 of the ’245 patent as unpatentable.