Intel Corp v. InterDigital Inc

1. Case Identification

• Case #: IPR2024-01441
• Patent #: 9,674,556
• Filed: September 17, 2024
• Petitioner(s): Intel Corporation
• Patent Owner(s): Interdigital, Inc.
• Challenged Claims: 1-8

2. Patent Overview

• Title: In-Loop Artifact Filtering
• Brief Description: The ’556 patent discloses methods and apparatuses for reducing video compression artifacts using a succession of at least two in-loop filters. The core embodiment involves applying a deblocking filter to reduce blocky artifacts, followed by an adaptive sparse de-noising filter to reduce other quantization noise.

3. Grounds for Unpatentability

Ground 1: Obviousness over Lee and AAPA - Claims 1-8 are obvious over Lee in view of Applicant Admitted Prior Art (AAPA).

• Prior Art Relied Upon: Lee (Application # 2003/0219073) and AAPA.
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner asserted that Lee teaches a video decoding method using successive in-loop filters: a deblocking filter for blockiness and a deringing filter for ringing artifacts. Lee also discloses selectively enabling these filters at the macroblock level. The AAPA, taken from the ’556 patent’s own specification, describes a known “adaptive sparse de-noising filter” designed to reduce general quantization noise more effectively than specialized filters. Petitioner argued that by replacing Lee’s deringing filter with the AAPA’s superior de-noising filter, all limitations of the challenged claims are met.
  • Motivation to Combine: A POSITA would combine Lee and the AAPA to improve overall video quality. Lee’s deblocking filter removes structured, non-random blocking artifacts, making the remaining noise a better match for the AAPA filter, which was designed for more random (i.i.d.) noise. This synergistic combination would yield the predictable result of more effective artifact removal than either filter could achieve alone. A POSITA would also be motivated to substitute the known element (Lee's deringing filter) with a superior known element (the AAPA filter) to achieve better performance.
  • Expectation of Success: Petitioner contended a POSITA would have a high expectation of success, as the combination involves applying a known, advanced filter to a known system to achieve a predictable improvement in noise reduction.

Ground 2: Obviousness over Chiang and Lin - Claims 1-8 are obvious over Chiang in view of Lin.

• Prior Art Relied Upon: Chiang (Application # 2006/0110062) and Lin (Application # 2003/0152146).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Chiang discloses an in-loop video decoding system that uses a deblocking filter followed by an "edge adaptive filter" to remove ringing artifacts. Under the Patent Owner's construction from a related proceeding, this edge adaptive filter constitutes an "adaptive sparse de-noising filter." Chiang also teaches selectively disabling its filter at the macroblock level by setting filter weights to zero. Lin teaches a method of conserving decoder resources by using flags, received from an encoder, to enable or disable in-loop filtering on a per-frame or per-sequence level.
  • Motivation to Combine: A POSITA would combine Lin’s explicit flag-based control with Chiang’s filtering system to improve efficiency. While Chiang’s method of setting weights to zero achieves disabling at a low level, Lin’s use of a high-level flag (e.g., sequence level) avoids the need for those calculations entirely, thus conserving significant processing resources. This represents a simple application of a known efficiency technique (Lin) to a known filtering system (Chiang).
  • Expectation of Success: Success would be expected because Chiang’s decoder already processes flags from the bitstream for other purposes, making the integration of Lin's filter control flag a straightforward and predictable modification.

Ground 3: Obviousness over VC1 Standard and Guleryuz - Claims 1-8 are obvious over the VC1 Standard in view of Guleryuz.

• Prior Art Relied Upon: VC1 Standard (SMPTE 421M-2006) and Guleryuz (a 2005 IEEE conference paper).
• Core Argument for this Ground:
  • Prior Art Mapping: The VC1 Standard describes a video decoding process that includes an in-loop deblocking filter and a LOOPFILTER flag to enable or disable it at the sequence level. Guleryuz discloses a high-performance nonlinear in-loop filter for reducing quantization noise, which Petitioner asserted is an "adaptive sparse denoising filter" under all proposed constructions.
  • Motivation to Combine: A POSITA would augment the VC1 Standard’s decoder by adding Guleryuz’s advanced denoising filter in succession after the standard’s deblocking filter. Using multiple in-loop filters was a common technique for improving decoded image quality. The existing LOOPFILTER flag in the VC1 Standard would be understood to control the entire in-loop filtering block, which would now include both the deblocking filter and the added Guleryuz filter, thus teaching the claimed selective enablement.
  • Expectation of Success: A POSITA would expect success in combining a known standard with a known, superior filtering technique to achieve the predictable result of improved image quality and noise reduction.

4. Key Claim Construction Positions

• "sparse de-noising filter": This term was the central focus of Petitioner's claim construction arguments.
  • Petitioner argued that during prosecution of the parent application, the applicant distinguished Lee by arguing Lee’s "deringing filter" was not a "sparse de-noising filter." Petitioner asserted this created an express disclaimer, such that the term must be construed to exclude deringing filters.
  • Petitioner highlighted that the Patent Owner has taken an inconsistent position in a co-pending ITC investigation, arguing there that the term is broad enough to encompass filters that perform deringing.
  • The petition advanced its invalidity arguments under several alternative constructions to demonstrate that the challenged claims are unpatentable regardless of the construction adopted by the Board.

5. Arguments Regarding Discretionary Denial

• §314(a) (Fintiv): Petitioner argued against discretionary denial under Fintiv, stating that the co-pending district court litigation is in its early stages, with trial scheduled for after the projected Final Written Decision (FWD) deadline. Furthermore, Petitioner noted that Fintiv factors do not apply to the parallel ITC investigation.
• §325(d): Petitioner contended that denial under §325(d) is inappropriate because the Examiner made clear errors during prosecution. Although Lee and the AAPA were previously considered, the Examiner erroneously allowed the claims after the applicant added the term "adaptive," even though both Lee's deringing filter and the AAPA's de-noising filter are inherently adaptive. Moreover, key references like Chiang, Lin, and the VC1 Standard were never applied by the Examiner, and Guleryuz was only cited in an IDS without substantive consideration.

6. Relief Requested

• Petitioner requests institution of an inter partes review and cancellation of claims 1-8 of Patent 9,674,556 as unpatentable.