PTAB

IPR2024-01488

MediaTek Inc v. Daedalus Prime LLC

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1. Case Identification

2. Patent Overview

  • Title: Asymmetric Performance Multicore Architecture with Same Instruction Set Architecture
  • Brief Description: The ’281 patent discloses an asymmetric multicore processor architecture featuring a first plurality of high-performance, high-power cores and a second plurality of lower-performance, low-power cores. Both sets of cores support the same instruction set architecture (ISA) to allow for dynamic management of performance and power consumption.

3. Grounds for Unpatentability

Ground 1A: Claims 1, 2, 4, 6, 8, 9, 11, 13, 15, 16, 18, and 20 are obvious over Sutardja in view of Mathieson.

  • Prior Art Relied Upon: Sutardja (Application # 2008/0288748) and Mathieson (Application # 2011/0213950).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Sutardja discloses the core architecture of the claimed invention, including a multi-core system with high-power (HP) and low-power (LP) cores, a shared L2 caching layer, and a power management system (PMS) module for enabling/disabling cores. Sutardja also taught that its HP cores are higher performance, consume more power, and operate at higher frequencies (e.g., >1 GHz) than its LP cores (e.g., <500 MHz), and that both core types can use the same ISA. Petitioner contended that while Sutardja discloses at least one LP core, Mathieson explicitly teaches using a plurality of "slow" cores to improve parallelism and power efficiency, thus rendering the claimed "second plurality of cores" obvious. The claimed operating system control was mapped to Sutardja’s kernel module, which monitors system demand and controls the core mix via the PMS module.
    • Motivation to Combine: A person of ordinary skill in the art (POSITA) would combine these references because both address the same problem of power management in multi-core processors for mobile devices. A POSITA would have been motivated to apply Mathieson’s teaching of using multiple low-power cores to Sutardja’s established architecture to predictably increase processing capacity at lower power, improve parallelism, and enable simpler task switching.
    • Expectation of Success: A POSITA would have a reasonable expectation of success, as the combination involves applying a known technique (duplicating low-power cores) to a known architecture to achieve predictable improvements in power consumption and performance.

Ground 2A: Claims 1-4, 6, 8-11, 13, 15-18, and 20 are obvious over Mathieson in view of Sakarda.

  • Prior Art Relied Upon: Mathieson (Application # 2011/0213950) and Sakarda (Patent 9,442,758).

  • Core Argument for this Ground:

    • Prior Art Mapping: Petitioner asserted that Mathieson discloses a multi-core processor with a first set of "fast" cores and a second set of "slow" cores, where the fast cores have higher performance and higher leakage power. Mathieson also discloses a shared resource unit (L2 cache) and a controller for switching between operating modes. Petitioner argued that Sakarda supplies the explicit teaching that all processor cores execute the same computer instructions to facilitate workload sharing. Furthermore, Sakarda teaches operating its slow cores in a lower frequency range (e.g., 30-100 MHz) than its fast cores (e.g., 100-800 MHz) to reduce power consumption, directly teaching the claimed limitation that the second plurality of cores has a maximum operating frequency less than that of the first.
    • Motivation to Combine: A POSITA would combine these references because they both seek to conserve power in multicore processors using fast and slow cores. A POSITA would incorporate Sakarda's teaching of a unified ISA into Mathieson's architecture to achieve the known benefits of easier workload sharing and more efficient core usage. Similarly, applying Sakarda's specific use of different frequency ranges to Mathieson's architecture would be an obvious way to further optimize the known goal of power conservation.
    • Expectation of Success: The combination would predictably result in a more efficient processor that conserves power by operating cores at appropriate frequencies, giving a POSITA a reasonable expectation of success.

  • Additional Grounds: Petitioner asserted additional obviousness challenges by adding a third reference to the primary combinations. These included:

    • Adding Patterson-1 (a computer architecture textbook) to teach splitting L1 caches into separate instruction and data caches (Ground 1B).
    • Adding Knebel (Application # 2009/0106494) to teach a system memory interface for searching memory after a cache miss (Grounds 1C and 2C).
    • Adding Liu (Application # 2006/0053258) to teach using coherency logic circuitry, such as a snoop filter, to maintain cache coherency in the shared caching layer (Grounds 1D and 2B).

4. Arguments Regarding Discretionary Denial

  • Petitioner argued that discretionary denial under Fintiv is unwarranted. It was asserted that the petition relies on materially different and non-cumulative prior art not applied during prosecution (Factor 6). Petitioner contended it acted diligently by filing the petition shortly after receiving the patent owner's infringement contentions in a parallel district court case (Factor 3), and that the petition challenges claims not asserted in that litigation (Factor 4). Petitioner argued that the district court trial date, while scheduled before the Final Written Decision (FWD) deadline, is not determinative and should be balanced against the other factors favoring institution.

5. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-21 of the ’281 patent as unpatentable under 35 U.S.C. §103.