Samsung Electronics Co Ltd v. Netlist Inc

1. Case Identification

• Case #: IPR2025-00002
• Patent #: 11,880,319
• Filed: October 24, 2024
• Petitioner(s): Samsung Electronics Co., Ltd.
• Patent Owner(s): Netlist, Inc.
• Challenged Claims: 1-20

2. Patent Overview

• Title: Memory Subsystem with an Open Drain Output for Communicating During an Initialization Operation
• Brief Description: The ’319 patent discloses a memory subsystem that uses an open-drain output to provide two distinct signaling interfaces. The first interface signals parity errors during normal operations, while a second, distinct interface provides status signals during a separate initialization operation, creating a handshake mechanism between the memory subsystem and a host controller.

3. Grounds for Unpatentability

Ground 1: Obviousness over Hazelzet and JEDEC - Claims 1-20 are obvious over Hazelzet in view of JEDEC.

• Prior Art Relied Upon: Hazelzet (Application # 2008/0098277) and JEDEC (a December 2009 JEDEC Committee Letter Ballot for LRDIMM DDR3 Memory).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Hazelzet disclosed the foundation of the invention: a memory module (RDIMM) with a memory subsystem controller having an open-drain output (the UE line) used to report parity or ECC errors during normal operations (the "first signaling interface"). JEDEC, a proposal for LRDIMM memory modules, taught adding data buffering and an initialization mode with various training sequences (e.g., MB-DRAM training). JEDEC explicitly disclosed using an open-drain ERROUT# pin to signal the completion of this training to the host, which Petitioner asserted constituted the claimed "second signaling interface." Petitioner contended that the JEDEC training operation was distinct from normal memory read/write operations, which were disabled until training was complete.
  • Motivation to Combine: A POSITA would combine these references to improve the performance and reliability of Hazelzet’s high-density RDIMM. Adding the data buffering and training taught by JEDEC was a known method to reduce electrical load and ensure reliable operation at higher speeds. A POSITA would be motivated to use Hazelzet's existing open-drain output for this new training status notification, as taught by JEDEC, to implement an efficient handshake mechanism, avoid polling, and conserve limited output pins.
  • Expectation of Success: Petitioner asserted that combining these known elements—data buffering, memory training, and open-drain signaling—would have been a straightforward implementation of existing technologies to achieve predictable improvements in memory system performance.

Ground 2: Obviousness over Hazelzet and Buchmann - Claims 1-20 are obvious over Hazelzet in view of Buchmann.

• Prior Art Relied Upon: Hazelzet (Application # 2008/0098277) and Buchmann (Patent 8,139,430).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground is similar to Ground 1, but used Buchmann as the source for the initialization and training teachings. Buchmann disclosed a memory module with a "SBC" (Side Band Communication) mode for performing training sequences (e.g., TS0, TS3) during startup, before high-speed normal operations began. Buchmann further taught generating notification signals, such as "TS_done," to inform the host that training was complete. Petitioner argued this notification, when implemented on Hazelzet's open-drain output, would constitute the "second signaling interface."
  • Motivation to Combine: The motivation was analogous to Ground 1: a POSITA would be motivated to incorporate Buchmann's training phase into Hazelzet's module to establish reliable communication before normal operation. This combination addressed the need for improved system reliability in high-density modules. Petitioner emphasized that the PTAB has repeatedly invalidated substantially similar claims in related Netlist patents over this same combination.
  • Expectation of Success: The combination involved applying Buchmann's known training techniques to Hazelzet's known memory module architecture, which Petitioner argued would have yielded the expected result of a more reliable system with a clear handshaking protocol for initialization.

Ground 3: Additive Obviousness over Grounds 1-3 in view of Kim - Claims 1-20 are obvious over the combinations of Grounds 1-3 further in view of Kim.

• Prior Art Relied Upon: Hazelzet in view of JEDEC, Buchmann, or Wang, further combined with Kim (Patent 8,359,521).

• Core Argument for this Ground:

  • Prior Art Mapping: Petitioner argued that to the extent the primary combinations did not render every limitation obvious, adding Kim would resolve any doubt. Kim disclosed a memory device with a shared error feedback pin (ERROR#) that explicitly used an OR-gate to combine multiple status signals (e.g., Parity error and CRC error) onto a single open-drain output.
  • Motivation to Combine: A POSITA, seeking to implement the training notifications from JEDEC or Buchmann onto Hazelzet’s existing error-reporting pin, would be motivated to use Kim's OR-gate logic. This represented a well-known, simple, and efficient technique for combining multiple signals onto a shared pin. It would allow the same open-drain output to report parity errors during normal operation and training status during initialization, directly teaching the logic circuit required for claim 8.
  • Key Aspects: This ground explicitly addressed the implementation of a logic circuit to manage the different signals for the first and second signaling interfaces on a single shared output pin.

• Additional Grounds: Petitioner asserted an additional obviousness challenge based on Hazelzet in view of Wang (Patent 8,386,722), which taught an interface circuit for data buffering and training to improve memory performance. This ground relied on similar motivations to combine as those for JEDEC and Buchmann.

4. Arguments Regarding Discretionary Denial

• Petitioner argued against discretionary denial under §325(d), asserting that the Examiner did not consider the specific prior art combinations presented in the petition. Although the Examiner considered Hazelzet with a different JEDEC reference, the specific grounds and arguments were not previously evaluated. Furthermore, Petitioner argued the Examiner materially erred by failing to analyze the claims in view of prior PTAB Final Written Decisions that canceled substantially similar claims in parent patents based on the same Hazelzet and Buchmann combination.
• Petitioner argued against discretionary denial under Fintiv, stating there is no parallel district court litigation where Netlist has asserted the ’319 patent against Samsung. Petitioner noted that it has only pursued a declaratory judgment of non-infringement.

5. Relief Requested

• Petitioner requests institution of inter partes review and cancellation of claims 1-20 of the ’319 patent as unpatentable.