PTAB

IPR2025-00213

Phison Electronics Corp v. Vervain LLC

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Lifetime Mixed Level Non-Volatile Memory System
  • Brief Description: The ’385 patent describes a hybrid non-volatile memory system comprising both Multi-Level Cell (MLC) and Single-Level Cell (SLC) memory modules. The system uses a Flash Translation Layer (FTL) to manage data placement between the two module types to improve system lifetime and endurance.

3. Grounds for Unpatentability

Ground 1: Claims 1-11 are obvious over Gavens in view of knowledge of the POSITA.

  • Prior Art Relied Upon: Gavens (Patent 8,634,240) and general knowledge of a Person of Ordinary Skill in the Art (POSITA) regarding well-known wear-leveling techniques.
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Gavens, a reference from the SanDisk patent portfolio, discloses a multi-modal NAND flash system with all the core elements of claim 1. Gavens teaches a memory system with an MLC portion and a more robust, lower-density portion operating in a binary or "SLC" mode. Its controller performs standard FTL functions, including address mapping. Crucially, Gavens discloses multiple error management schemes, including a post-write-read process that functions as a "data integrity test." Upon detecting a threshold number of errors in the MLC portion, data is re-written to the more robust SLC-mode portion, meeting limitation [1e]. Gavens also discloses tracking the age of each block via an erase/program "hot count," which meets the limitation of counting block accesses [1f].
    • Motivation to Combine: Petitioner contended that Gavens teaches the benefits of using an SLC-like partition for data integrity and end-of-life management. A POSITA would be motivated to combine Gavens’s error management system with well-known wear-leveling techniques (such as moving frequently written data to the more durable SLC portion) for the common and predictable purpose of avoiding premature system failure and extending device lifetime.
    • Expectation of Success: A POSITA would have a high expectation of success in implementing known wear-leveling algorithms in the Gavens system, as such techniques were standard in the art for managing hybrid memory.

Ground 2: Claims 1-11 are obvious over Moshayedi in view of knowledge of the POSITA.

  • Prior Art Relied Upon: Moshayedi (Application # 2009/0327591) and, for the data integrity limitation, knowledge of error management techniques such as those in Gavens.
  • Core Argument for this Ground:
    • Prior Art Mapping: Moshayedi discloses a complete hybrid NAND flash system with distinct SLC and MLC memory modules and a controller performing FTL functions. Moshayedi explicitly teaches wear-leveling by tracking the number of times data for each logical block address (LBA) has been written and directing new data for high-write-count LBAs to the SLC flash. This directly teaches the "frequent writes" limitations [1f] and [1g]. For the "data integrity test" limitation [1e], Moshayedi discloses tracking data read errors and relocating data from blocks with accumulating errors to "blocks with less wear," which a POSITA would understand to be SLC blocks.
    • Motivation to Combine: Moshayedi's primary purpose is to avoid premature failure through wear-leveling. Petitioner asserted a POSITA would be motivated to supplement Moshayedi’s wear-leveling system with other known error management techniques (such as the post-write-read checks in Gavens) to create a more robust system, as both approaches address the same known problem of flash memory degradation.
    • Expectation of Success: A POSITA would expect success in combining these known techniques, as controllers were routinely designed to implement multiple, compatible algorithms for memory management.

Ground 3: Claims 1-11 are obvious over Sutardja in view of knowledge of the POSITA.

  • Prior Art Relied Upon: Sutardja (Application # 2008/0140918) and, for enhancing the data integrity test, knowledge of error management techniques such as those in Gavens.

  • Core Argument for this Ground:

    • Prior Art Mapping: Sutardja discloses a hybrid solid-state memory system with a first (MLC) and second (SLC) non-volatile memory. Its controller performs FTL functions and various wear-leveling analyses. Sutardja teaches mapping logical addresses with high write frequencies to the higher endurance SLC memory, meeting limitations [1f] and [1g]. It also discloses a "degradation test" on the MLC memory that estimates its remaining life cycle; if the test indicates near end-of-life ("fails"), the system remaps writes to the SLC memory, satisfying the data integrity test limitation [1e].
    • Motivation to Combine: The motivation is inherent in Sutardja’s disclosure: to use a combination of wear monitoring and preferential data placement to extend the life of the memory system. Petitioner argued that applying additional, known error-management techniques to Sutardja's system would have been an obvious path to further improve its reliability.
    • Expectation of Success: A POSITA would have reasonably expected success in implementing different or additional data integrity tests within the framework taught by Sutardja to achieve the same goal of preventing data loss and premature failure.

  • Additional Grounds: Petitioner asserted that dependent claims 12-15 are also obvious for reasons similar to those for claim 1, as they recite conventional aspects of flash memory systems, such as adding an HDD or moving less-frequently accessed data to the MLC module.

4. Key Claim Construction Positions

  • "MLC non-volatile memory module" / "SLC non-volatile memory module": Petitioner argued these terms must be construed to mean physically distinct modules with different underlying circuitry. This is based on their established meanings to a POSITA and the patent’s explicit references to separate modules. Petitioner contended this construction excludes systems that use a single MLC memory chip operating in different modes (e.g., a "pseudo-SLC" mode), a distinction critical to differentiating the claimed invention from certain prior art configurations.

5. Arguments Regarding Discretionary Denial

  • Petitioner argued that discretionary denial under Fintiv is unwarranted. The parallel district court litigation against Petitioner is in a very early stage, with no substantive rulings issued and the claim construction hearing postponed. Petitioner asserted that the merits of the IPR are strong and that institution would serve system efficiency and fairness by resolving substantial patentability questions for a patent family asserted across multiple litigations.

6. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-15 of Patent 9,196,385 as unpatentable under 35 U.S.C. §103.