PTAB

IPR2025-00214

Phison Electronics Corp v. Vervain LLC

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1. Case Identification

2. Patent Overview

  • Title: Lifetime Mixed Level Non-Volatile Memory System
  • Brief Description: The ’240 patent discloses a hybrid non-volatile memory system combining Multi-Level Cell (MLC) and Single-Level Cell (SLC) NAND flash modules. A controller manages data placement to improve endurance by preferentially directing data to the more robust SLC module based on data integrity test failures or wear-leveling algorithms that track write frequency.

3. Grounds for Unpatentability

Ground 1: Claims 1-10 are obvious over Gavens in view of the knowledge of a POSITA.

  • Prior Art Relied Upon: Gavens (Patent 8,634,240) and its incorporated references.
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Gavens discloses a complete multi-modal NAND flash system with a controller performing error management. Gavens teaches an MLC memory that can operate in a binary (SLC-like or pSLC) mode. Its controller performs a post-write-read check by comparing written data to a cached original; if errors exceed a threshold, data is rewritten to the more robust, lower-density (pSLC) portion. Petitioner asserted this maps to the claimed "data integrity test" and remapping function. Gavens also teaches tracking the age of each block using a "hot count" (erase/program cycles), which Petitioner contended meets the claim limitation of determining frequently accessed blocks for segregation.
    • Motivation to Combine: Petitioner contended a person of ordinary skill in the art (POSITA) would be motivated to substitute a true, physically distinct SLC module for Gavens's pSLC-mode memory to achieve even greater endurance and reliability, a well-known objective in the field. A POSITA would also combine Gavens’s end-of-life error management with known, conventional wear-leveling techniques to create a more robust system and avoid premature failure.
    • Expectation of Success: Combining these known elements—a true SLC module for a pSLC portion and standard wear-leveling logic—was argued to be a straightforward application of known solutions to achieve the predictable result of improved system lifetime.

Ground 2: Claims 1-10 are obvious over Moshayedi in view of the knowledge of a POSITA.

  • Prior Art Relied Upon: Moshayedi (Application # 2009/0327591).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner asserted Moshayedi teaches a hybrid flash storage device with distinct SLC and MLC memory modules. Moshayedi's controller performs wear-leveling by maintaining write counts for logical blocks and erase counts for physical blocks. This data is used to segregate "hot" (frequently written) data to SLC memory and "cold" data to MLC memory. This was argued to meet the "segregate" and "determine" limitations. Moshayedi further discloses that when a block accumulates a high number of read errors, its data is relocated to a "block with less wear" (i.e., an SLC block), which Petitioner mapped to the "data integrity test" limitation. The transfer of data occurs when an erase count reaches a predetermined threshold (e.g., "500"), satisfying the "transfer after reaching the predetermined count value" limitation.
    • Motivation to Combine: Moshayedi is primarily directed at wear-leveling. Petitioner argued a POSITA, seeking to build a comprehensive solution to avoid premature failure, would be motivated to implement Moshayedi's wear-leveling system alongside known end-of-life error management techniques, such as the post-write-read checks taught by Gavens, to enhance data reliability.
    • Expectation of Success: Because both wear-leveling and error management were common techniques for improving flash memory endurance, a POSITA would have a high expectation of success in combining their functionalities.

Ground 3: Claims 1-10 are obvious over Sutardja in view of the knowledge of a POSITA.

  • Prior Art Relied Upon: Sutardja (Application # 2008/0140918).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued Sutardja discloses a hybrid solid-state memory system using both lower-density (SLC) and higher-density (MLC) non-volatile memory. Sutardja's controller employs multiple wear-leveling schemes, including tracking write frequencies of logical addresses to map "hot" data to the more robust SLC memory, thereby satisfying the "segregate" limitation. Sutardja also teaches a "degradation test" that periodically assesses a block's health by writing and reading back data over time. If degradation exceeds a threshold (failing the "data integrity test"), the system remaps writes to the healthier (SLC) memory. This process, which occurs based on reaching wear thresholds, was argued to meet the transfer "on a periodic basis" after reaching a "predetermined count value."
    • Motivation to Combine: Sutardja itself was presented as already teaching the combination of wear-leveling (based on write frequency) and a form of data integrity testing (the degradation test) for the express purpose of extending system lifetime. Petitioner contended a POSITA would find Sutardja's teachings to render the claimed invention obvious, or would be motivated to supplement Sutardja with other known error management techniques for even greater reliability.
    • Expectation of Success: As Sutardja provides a detailed framework for managing a hybrid memory system, a POSITA would expect that implementing the claimed functions based on its disclosure would be successful.

4. Key Claim Construction Positions

  • Petitioner argued that the terms "MLC non-volatile memory module" and "SLC non-volatile memory module" refer to physically distinct memory modules with different underlying circuitry, as understood by a POSITA. This construction is central to the argument that substituting a true SLC module for a pSLC region in a reference like Gavens would be obvious.
  • Petitioner maintained that several other key terms—including "Blocks," "Controller," and "Data Integrity Test"—are ambiguous or indefinite as claimed but asserted that the prior art discloses the claimed functions even under a broad interpretation of these terms.

5. Arguments Regarding Discretionary Denial

  • Petitioner argued against discretionary denial under the Fintiv factors. It contended that the petition was filed expeditiously after service of the complaint in the parallel district court litigation. Petitioner asserted the parallel case is in an early stage, with no substantive rulings, a claim construction hearing not yet held, and limited discovery. It was argued that the IPR provides a more efficient and comprehensive forum for resolving the invalidity questions than the district court, and that the strong merits of the petition weigh in favor of institution for the public interest.

6. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-10 of the ’240 patent as unpatentable under 35 U.S.C. §103.