PTAB

IPR2025-00215

Phison Electronics Corp v. Vervain LLC

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Key Events
Petition

1. Case Identification

2. Patent Overview

  • Title: LIFETIME MIXED LEVEL NON-VOLATILE MEMORY SYSTEM
  • Brief Description: The ’300 patent describes a hybrid non-volatile memory system using both multi-level cell (MLC) and single-level cell (SLC) NAND flash memory. The invention purports to increase the lifetime and reliability of the memory system through a controller that performs a "data integrity test" and wear-leveling operations, remapping data between MLC and SLC portions based on access frequency or data errors.

3. Grounds for Unpatentability

Ground 1: Obviousness of Claims 1-12 over Gavens and Incorporated References

  • Prior Art Relied Upon: Gavens (Patent 8,634,240), supplemented by its incorporated references and the general knowledge of a person of ordinary skill in the art (POSITA), with additional context from references including Lee (Patent 8,078,794), Sutardja (Application # 2008/0140918), and Moshayedi (Application # 2009/0327591).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that the ’300 patent claims are an abstract and unsupported rewriting of a known hybrid memory system architecture. The primary reference, Gavens, discloses a multi-modal NAND flash memory system capable of operating portions of its MLC memory in a more robust, single-bit "binary" or pseudo-SLC (pSLC) mode. This establishes the claimed hybrid MLC and SLC nonvolatile memory elements.
    • Petitioner asserted that the critical "data integrity test" of independent claims 1 and 12 is taught by Gavens's post-write-read error management scheme. In Gavens, after data is written to the higher-density MLC portion (a "first copy"), it is compared against the "original copy which may be cached" in Random Access Volatile Memory (RAVM). If the number of error bits in the stored data exceeds a threshold, the original data from the cache is rewritten to the more robust, lower-density pSLC portion. This process directly maps to the claimed limitations of performing a data integrity test by comparing stored data to retained data in volatile memory and, upon failure, remapping and transferring the data to an area with enhanced endurance (the SLC/pSLC space). The claimed RAVM is disclosed by references incorporated into Gavens, which teach using SRAM or DRAM within a controller for caching and buffering.
    • Dependent claim limitations were also argued to be obvious. For example, claim 10's requirement for periodically moving frequently accessed data from MLC to SLC space was described as a well-known wear-leveling technique taught by references like Lee, Sutardja, and Moshayedi.
    • Motivation to Combine: Petitioner contended that a POSITA would be motivated to modify the Gavens system by substituting a "native" SLC memory module for Gavens's pSLC portion. The motivation was simple and compelling: to achieve the well-known and predictable benefits of superior endurance and performance that native SLC provides over pSLC. This modification was presented as a straightforward substitution of one known component for another to improve a known characteristic (endurance). Similarly, a POSITA would be motivated to implement the wear-leveling strategies of Lee or Sutardja in the Gavens system to solve the recognized problem of premature failure due to uneven block usage in NAND flash memory.
    • Expectation of Success: A POSITA would have had a high expectation of success in making these combinations. Substituting native SLC for pSLC would integrate into the existing flash controller architecture with predictable results. Implementing known wear-leveling algorithms was a common practice in flash memory system design to enhance device lifetime, a primary goal of the ’300 patent itself.

4. Key Claim Construction Positions

  • Petitioner argued that several key terms, which were introduced late in the prosecution of the ’300 patent, must be construed in the context of established NAND flash technology to avoid being indefinite. These constructions were presented as critical to mapping the prior art.
    • "MLC/SLC non-volatile memory": Proposed constructions distinguish the two based on their fundamental architectural capability. "MLC memory" was defined as circuitry capable of storing multiple logical pages in a single physical page, whereas "SLC memory" is incapable of doing so.
    • "memory element": Argued to mean a physical, addressable unit within the flash memory, such as a "physical flash memory block," rather than an individual storage cell.
    • "memory space": Contended to mean the "logical address space" that is mapped by the controller to the physical memory elements. This construction is crucial because it clarifies that the patent is claiming operations on logical data constructs, which are then implemented on the physical hardware disclosed in the prior art.

5. Arguments Regarding Discretionary Denial

  • Petitioner argued that discretionary denial under the Fintiv factors would be inappropriate. The core arguments were:
    • The parallel litigation in the Western District of Texas was in a very early stage. At the time of filing, no Markman hearing had occurred, and fact discovery had not substantially progressed.
    • The petition presents a strong, compelling case for unpatentability on the merits.
    • Institution would promote system efficiency by simplifying the complex district court litigation, which involves eight patents from the same family with similar specifications but varying claim language. An IPR decision would resolve patentability questions more efficiently than the district court.

6. Relief Requested

  • Petitioner requested institution of an inter partes review and cancellation of claims 1-12 of Patent 10,950,300 as unpatentable under 35 U.S.C. §103.