PTAB

IPR2025-00223

Advanced Micro Devices Inc v. XtreamEdge Inc

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Key Events
Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Programmable Device for Data Flow Processing
  • Brief Description: The ’943 patent describes a programmable logic device (PLD), such as an FPGA, for use in user-configurable servers. The device is structured with two regions: a first region containing a hardware-based router and a lockable bridge to control access, and a second region containing one or more user-definable "sandboxes" with programmable electronic circuits.

3. Grounds for Unpatentability

Ground 1: Obviousness over Seshadri and Biederman - Claims 1-5, 9-14, and 18 are obvious over Seshadri in view of Biederman.

  • Prior Art Relied Upon: Seshadri (Patent 10,776,142) and Biederman (Application # 2018/0191642).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued Seshadri taught the core limitations of the ’943 patent, including an FPGA architecture used in scalable computing environments with two distinct regions: a "shell logic" region (claimed first region) and a "client configurable circuit" region (claimed second region). Seshadri’s shell logic allegedly performed routing and bridging functions and included functionality to "isolate a configuration access port" to lock/unlock user access for reprogramming, thereby teaching the lockable bridge. For claims requiring a plurality of sandboxes, Petitioner asserted that Biederman, which taught partitioning an FPGA's programmable fabric into multiple, dynamically resizable partitions for different users or tasks, supplied this missing element.
    • Motivation to Combine: A POSITA would combine Seshadri's secure, two-region FPGA architecture with Biederman's well-known technique for multi-tenant partitioning. This combination would predictably result in an FPGA that could securely serve multiple users by partitioning Seshadri’s client-configurable area into distinct, resizable sandboxes as taught by Biederman, improving resource utilization in a cloud environment.
    • Expectation of Success: A POSITA would have a reasonable expectation of success because the combination involved applying a known partitioning method (Biederman) to a known FPGA architecture (Seshadri) to achieve the predictable benefits of multi-tenancy without changing the fundamental operation of either reference.

Ground 2: Obviousness over Atsatt-113 and Biederman - Claims 1-5, 9-14, and 18 are obvious over Atsatt-113 in view of Biederman.

  • Prior Art Relied Upon: Atsatt-113 (Application # 2019/0095113) and Biederman (Application # 2018/0191642).
  • Core Argument for this Ground:
    • Prior Art Mapping: As an alternative to Seshadri, Petitioner argued Atsatt-113 disclosed a "sectorized FPGA" with a control area region (claimed first region) and a region of programmable logic sectors (claimed second region). The control area included global resources that routed data signals and managed access to user partitions. Petitioner contended that Atsatt-113’s use of an "authentication key" and "masks" to control access to different user partitions constituted a lockable/unlockable bridge. As in the previous ground, Biederman was cited for its teaching of dynamically resizing multiple partitions (sandboxes) to meet processing needs, a feature not explicitly taught in Atsatt-113.
    • Motivation to Combine: A POSITA would combine Atsatt-113’s architecture, which already provided for multiple user partitions of varying sizes, with Biederman’s specific teachings on dynamically adjusting partition sizes. This would be a predictable improvement, adding flexibility to Atsatt-113's static partitioning to maximize resource utilization and reduce costs in a multi-tenant FPGA environment.
    • Expectation of Success: The combination would have a high expectation of success as it involved adding a known technique for dynamic partition sizing (Biederman) to a device already designed for multi-partition use (Atsatt-113), yielding the expected benefit of improved flexibility.

Ground 3: Obviousness over Core Art and Tarafdar - Claims 6 and 15 are obvious over the combinations in Grounds 1-4 in view of Tarafdar.

  • Prior Art Relied Upon: Seshadri or Atsatt-113 (with or without Biederman), and Tarafdar ("Enabling Flexible Network FPGA Clusters in a Heterogeneous Cloud Data Center," FPGA’17).

  • Core Argument for this Ground:

    • Prior Art Mapping: Petitioner asserted that claims 6 and 15 require the router to perform analytics on device resources, including determining communication bandwidth and resource utilization. Tarafdar allegedly taught this limitation by disclosing "Cloud Cluster Management Tools" that perform analytics on FPGA resources (performance, resource utilization, CPU usage) to orchestrate and load-balance FPGA modules. Petitioner argued that Tarafdar’s "hypervisor" region, analogous to the first region of Seshadri and Atsatt-113, would be the obvious location to perform this monitoring.
    • Motivation to Combine: A POSITA would be motivated to apply Tarafdar’s analytics and monitoring techniques to the FPGA systems of Seshadri or Atsatt-113 to improve administration and efficiency. Implementing these known management tools would provide the recognized benefits of reliable performance and better orchestration of large FPGA clusters in a data center, a predictable improvement.
    • Expectation of Success: Success was reasonably expected because it involved adding a known monitoring function (Tarafdar) to an existing FPGA architecture to gain well-understood performance benefits.

  • Additional Grounds: Petitioner asserted additional obviousness challenges based on the primary combinations in view of Kulkarni (Patent 8,015,386) for claims requiring configurable port interfaces (claims 7 and 16) and Atsatt-923 (Application # 2019/0041923) for claims requiring clock cycle utilization regulation for power/thermal control (claims 8 and 17).

4. Key Claim Construction Positions

  • "programmable logic device": Petitioner proposed this term means "an IC where the user can alter the connection pattern of the circuits." This construction was based on the specification, prosecution history, and conventional meaning. Petitioner argued that while this construction is relevant, each ground teaches a PLD even without its adoption.

5. Arguments Regarding Discretionary Denial

  • Petitioner argued discretionary denial is unwarranted. Under Fintiv, the parallel district court case is in its early stages, with claim construction not yet briefed and a trial date set for May 2026. Under §325(d), denial is inappropriate because the prior art references asserted in the petition (Seshadri, Biederman, Atsatt-113, Tarafdar, Kulkarni, and Atsatt-923) were not cited or considered during the original prosecution.

6. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-18 of the ’943 patent as unpatentable.