PTAB

IPR2025-00515

SanDisk Technologies Inc v. Polaris PowerLED Technologies LLC

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Key Events
Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Adaptive Error Correction Coding
  • Brief Description: The ’085 patent is directed to memory systems, such as flash memory, that adaptively select an error correction coding (ECC) scheme from a plurality of schemes ("gears") based on a determined bit error rate to address memory degradation over its lifetime.

3. Grounds for Unpatentability

Ground 1: Claims 1-2, 4-5, 14-17, 22-25, and 29-33 are obvious over Li in view of Cideciyan.

  • Prior Art Relied Upon: Li (Application # 2014/0136927) and Cideciyan (Patent 9,037,951).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Li, the primary reference, teaches the core invention: a system that adaptively selects an ECC scheme for a "portion" of flash memory based on a determined bit error rate (BER). However, Petitioner contended that two limitations, added during prosecution to secure allowance, are disclosed by Cideciyan. First, Cideciyan’s product-code ECC scheme, which uses primary (C1) and secondary (C2) component codes, teaches a region storing a data payload with corresponding primary and secondary ECC parity symbols. Second, Cideciyan’s architecture, which stores data in groups of pages distributed across multiple parallel channels, teaches a region where two or more flash memory pages can be read simultaneously.
    • Motivation to Combine: A person of ordinary skill in the art (POSITA) would combine Li and Cideciyan to implement Li’s general adaptive ECC framework with a specific, well-known, and robust ECC scheme (Cideciyan's product code) to improve error recovery. Furthermore, a POSITA would have been motivated to use Cideciyan's parallel channel architecture to improve the performance of Li's system, as achieving high performance through parallelism was a known goal in solid-state drive (SSD) design. Both references describe similar flash-based storage systems with similar objectives of improving reliability and performance.
    • Expectation of Success: A POSITA would have had a reasonable expectation of success because the combination merely applies known techniques (product codes, parallel data striping) to a known system (adaptive ECC flash memory) to achieve the predictable benefits of improved error correction and faster read/write performance.

Ground 2: Claims 1-2, 4-5, 14-17, 22-25, and 29-33 are obvious over Li in view of Cideciyan and Frost.

  • Prior Art Relied Upon: Li (Application # 2014/0136927), Cideciyan (Patent 9,037,951), and Frost (Patent 8,176,360).

  • Core Argument for this Ground:

    • Prior Art Mapping: This ground builds upon Ground 1 by adding Frost to explicitly address the "read simultaneously" limitation. Petitioner argued that to the extent Cideciyan’s teaching of "parallel access" across channels might be viewed as not explicitly teaching simultaneous reads, Frost provides this missing detail. Frost describes a flash-based storage system where a controller accesses memory chips on individual "Lanes" (channels) "at, or very nearly at, the same time," and explicitly states that pages in a page stripe can be read "simultaneously or near-simultaneously."
    • Motivation to Combine: A POSITA implementing the parallel architecture of the Li and Cideciyan combination would have been motivated to incorporate Frost's teachings as a conventional and well-known method for achieving simultaneous access. This would provide the obvious and predictable benefit of faster read operations, a primary goal in SSD design.
    • Expectation of Success: The combination would have been successful and predictable because it involves applying a known technique for simultaneous data access (Frost) to a system already configured for parallel access (Li/Cideciyan) to achieve the expected result of increased performance.

  • Additional Grounds: Petitioner asserted additional obviousness challenges for claims 6-7 and 18 based on combinations that further included Leung (Application # 2008/0222490). Leung was cited for its teaching of selecting an ECC gear that has the highest data payload size while still meeting a predetermined acceptable uncorrectable bit error rate (aUBER).

4. Key Claim Construction Positions

  • "gear" (claim 1): Petitioner argued a POSITA would understand from the specification that a "gear" is a set of parameters specifying an ECC scheme. This includes parameters like payload capacity, component code types, and thresholds (e.g., BER thresholds) used to determine when that gear is appropriate. This construction is central to mapping Li's teaching of selecting ECC schemes based on thresholds to the claims.
  • Means-Plus-Function Terms (claims 24-25): Petitioner identified several means-plus-function terms and asserted that the corresponding structures are disclosed in the specification, such as an integrated circuit or specific hardware blocks within an SSD controller that perform the claimed functions of determining, comparing, and selecting.

5. Arguments Regarding Discretionary Denial

  • Fintiv Factors: Petitioner argued against discretionary denial under Fintiv, stating that the factors favor institution. Key reasons included that the scheduled trial date in the parallel district court litigation (June 2026) is well after the projected date for a Final Written Decision (FWD) in the IPR (July 2026). Petitioner also asserted that investment in the parallel litigation has been minimal, with no schedule set and a Markman hearing unlikely before an institution decision.
  • Advanced Bionics Test (§325(d)): Petitioner argued that denial under §325(d) is not warranted because the current challenges are not cumulative of art considered during prosecution. Specifically, the key secondary references (Cideciyan, Frost, and Leung) were never considered by the Examiner. Petitioner contended the Examiner materially erred by overlooking art that taught the very limitations added during prosecution to overcome prior art rejections.

6. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-2, 4-7, 14-18, 22-25, and 29-33 of the ’085 patent as unpatentable under 35 U.S.C. §103.