Sandisk Technologies Inc v. Polaris PowerLED Technologies LLC

Prosecution History analysis

Examiner Search analysis

Invalidity Framework analysis

Petition

Petition Analysis

## 1. Case Identification
- Case Number: [IPR2025-00515](https://ai-lab.exparte.com/case/ptab/IPR2025-00515)
- Patent #: [9,183,085](https://ai-lab.exparte.com/patent/9183085)
- Filed: January 29, 2025
- Petitioner(s): [SanDisk Technologies, Inc.](https://ai-lab.exparte.com/party/sandisk-corp) and [Western Digital Technologies, Inc.](https://ai-lab.exparte.com/party/western-digital-corp)
- Patent Owner(s): [Polaris Powerled Technologies, LLC](https://ai-lab.exparte.com/party/polaris-powerled-technologies-llc)
- Challenged Claims: 1-2, 4-7, 14-18, 22-25, and 29-33

## 2. Patent Overview
- Title: Adaptive Error Correction Coding Based on Data Error Rate
- Brief Description: The [’085](https://ai-lab.exparte.com/case/ptab/IPR2025-00515/doc/1001) patent is directed to flash memory systems that adaptively select an Error Correction Coding (ECC) scheme from a plurality of schemes ("gears") based on an observed bit error rate (BER) to counteract memory degradation over the device's lifetime.

## 3. Grounds for Unpatentability

#### Ground 1: Claims 1-2, 4-5, 14-17, 22-25, and 29-33 are obvious over Li in view of Cideciyan.
- **Prior Art Relied Upon:** Application # 2014/0136927 to Li et al. ([Li](https://ai-lab.exparte.com/case/ptab/IPR2025-00515/doc/1005)) and U.S. Patent No. [9,037,951](https://ai-lab.exparte.com/case/ptab/IPR2025-00515/doc/1006) to Cideciyan et al. ([Cideciyan](https://ai-lab.exparte.com/case/ptab/IPR2025-00515/doc/1006)).
- **Core Argument for this Ground:**
    - **Prior Art Mapping:** Petitioner argued that [Li](https://ai-lab.exparte.com/case/ptab/IPR2025-00515/doc/1005) teaches the core invention: a flash memory system that adaptively selects an ECC scheme for a "portion" of memory based on a determined BER. Petitioner asserted that [Cideciyan](https://ai-lab.exparte.com/case/ptab/IPR2025-00515/doc/1006), which was not before the Examiner, supplies the two key limitations added during prosecution to overcome prior art rejections. First, [Cideciyan](https://ai-lab.exparte.com/case/ptab/IPR2025-00515/doc/1006) taught storing a data payload with both primary (C1) and secondary (C2) ECC parity symbols using a product code scheme. Second, [Cideciyan](https://ai-lab.exparte.com/case/ptab/IPR2025-00515/doc/1006) taught organizing data into groups of pages (a "region" or "stride") distributed across multiple parallel channels, which Petitioner contended inherently teaches or suggests that the pages can be read simultaneously.
    - **Motivation to Combine:** A person of ordinary skill in the art (POSITA) would combine [Li](https://ai-lab.exparte.com/case/ptab/IPR2025-00515/doc/1005) and [Cideciyan](https://ai-lab.exparte.com/case/ptab/IPR2025-00515/doc/1006) to improve the performance and reliability of [Li](https://ai-lab.exparte.com/case/ptab/IPR2025-00515/doc/1005)’s adaptive ECC system. [Cideciyan](https://ai-lab.exparte.com/case/ptab/IPR2025-00515/doc/1006) taught a well-known product-code ECC scheme that provided superior error protection and performance benefits through channel-level parallelism. As [Cideciyan](https://ai-lab.exparte.com/case/ptab/IPR2025-00515/doc/1006) is from a major storage provider (IBM), a POSITA would have looked to such a reference to implement the generic adaptive ECC framework disclosed in [Li](https://ai-lab.exparte.com/case/ptab/IPR2025-00515/doc/1005).
    - **Expectation of Success:** A POSITA would have had a reasonable expectation of success because the combination involved applying a known, high-performance ECC and data organization technique ([Cideciyan](https://ai-lab.exparte.com/case/ptab/IPR2025-00515/doc/1006)) to a known type of system ([Li](https://ai-lab.exparte.com/case/ptab/IPR2025-00515/doc/1005)) to achieve the predictable benefits of improved error correction and parallel performance.

#### Ground 2: Claims 1-2, 4-5, 14-17, 22-25, and 29-33 are obvious over Li, Cideciyan, and Frost.
- **Prior Art Relied Upon:** [Li](https://ai-lab.exparte.com/case/ptab/IPR2025-00515/doc/1005), [Cideciyan](https://ai-lab.exparte.com/case/ptab/IPR2025-00515/doc/1006), and U.S. Patent No. [8,176,360](https://ai-lab.exparte.com/case/ptab/IPR2025-00515/doc/1007) to Frost et al. ([Frost](https://ai-lab.exparte.com/case/ptab/IPR2025-00515/doc/1007)).
- **Core Argument for this Ground:**
    - **Prior Art Mapping:** This ground reinforced the arguments of Ground 1, with [Frost](https://ai-lab.exparte.com/case/ptab/IPR2025-00515/doc/1007) added to explicitly teach the "simultaneously read" limitation. Petitioner argued that to the extent [Cideciyan](https://ai-lab.exparte.com/case/ptab/IPR2025-00515/doc/1006)'s teaching of "parallel access" is not viewed as explicitly teaching simultaneous reading, [Frost](https://ai-lab.exparte.com/case/ptab/IPR2025-00515/doc/1007) remedied any deficiency. [Frost](https://ai-lab.exparte.com/case/ptab/IPR2025-00515/doc/1007) described a flash-based storage system where a controller accesses memory chips corresponding to individual "Lanes" (channels) "at, or very nearly at, the same time" and that pages in a "page stripe" can be read "simultaneously or near-simultaneously."
    - **Motivation to Combine:** A POSITA, having decided to implement [Li](https://ai-lab.exparte.com/case/ptab/IPR2025-00515/doc/1005)'s system using [Cideciyan](https://ai-lab.exparte.com/case/ptab/IPR2025-00515/doc/1006)'s parallel channel architecture, would have been motivated to look to a reference like [Frost](https://ai-lab.exparte.com/case/ptab/IPR2025-00515/doc/1007) for a conventional and explicit implementation of simultaneous read operations to maximize the performance benefits of parallelism.
    - **Expectation of Success:** The combination merely applied a known technique (simultaneous page reads across channels) to a known device architecture to yield the predictable result of faster read operations.

- **Additional Grounds:** Petitioner asserted additional obviousness challenges (Grounds 3 and 4) against dependent claims 6-7 and 18. These grounds added Application # [2008/0222490](https://ai-lab.exparte.com/case/ptab/IPR2025-00515/doc/1008) to Leung et al. ([Leung](https://ai-lab.exparte.com/case/ptab/IPR2025-00515/doc/1008)) to the combinations of Grounds 1 and 2, respectively. [Leung](https://ai-lab.exparte.com/case/ptab/IPR2025-00515/doc/1008) was cited for its teaching of selecting an ECC gear that maximizes data payload size while satisfying a predetermined acceptable uncorrectable bit error rate (aUBER), which mapped directly to the limitations of the challenged dependent claims.

## 4. Key Claim Construction Positions
- **"gear" (claim 1):** Petitioner argued this term is explicitly defined in the [’085](https://ai-lab.exparte.com/case/ptab/IPR2025-00515/doc/1001) patent’s specification as "a set of parameter(s) specifying an error correction coding scheme," including payload capacity, code types, interleaving schemes, and thresholds for determining when the gear is appropriate. This construction was central to Petitioner's argument that the prior art's various ECC schemes with different parameters and performance thresholds met the definition of the claimed "gears."
- **Means-Plus-Function Terms (claims 24-25):** Petitioner identified several means-plus-function terms in claims 24 and 25, proposing that the corresponding structure for these functions was a circuit, such as the SSD controller and its constituent components (e.g., ECC 261, Error Statistics block 180) disclosed in the prior art.

## 6. Arguments Regarding Discretionary Denial
- Petitioner argued that discretionary denial under §314(a) based on *Fintiv* factors would be inappropriate. The scheduled trial date in the parallel district court litigation (June 16, 2026) was after the projected date for a Final Written Decision (FWD) in the IPR (July 2026). Petitioner also asserted that investment in the parallel case was minimal, the extent of issue overlap was speculative at this early stage, and the petition presented compelling evidence of unpatentability.
- Petitioner also argued that denial under §325(d) was not warranted under the *Advanced Bionics* test. The challenges were not cumulative because the key secondary references ([Cideciyan](https://ai-lab.exparte.com/case/ptab/IPR2025-00515/doc/1006), [Frost](https://ai-lab.exparte.com/case/ptab/IPR2025-00515/doc/1007), [Leung](https://ai-lab.exparte.com/case/ptab/IPR2025-00515/doc/1008)) were never considered by the Examiner. Petitioner contended the Examiner materially erred by allowing claims based on limitations (simultaneous reads, product codes) that were, in fact, well-known in the art as taught by the new prior art combinations.

## 7. Relief Requested
- Petitioner requested institution of an inter partes review and cancellation of claims 1-2, 4-7, 14-18, 22-25, and 29-33 of the [’085](https://ai-lab.exparte.com/case/ptab/IPR2025-00515/doc/1001) patent as unpatentable.

SanDisk & WD challenge adaptive ECC patent: 21 claims obvious over prior art teaching parallel flash memory access & simultaneous page reads.