Apple Inc v. ImberaTek LLC

1. Case Identification

• Case #: IPR2025-00575
• Patent #: 7,609,527
• Filed: February 6, 2025
• Petitioner(s): Apple Inc.
• Patent Owner(s): ImberaTek LLC
• Challenged Claims: 1-27

2. Patent Overview

• Title: ELECTRONIC MODULE
• Brief Description: The ’527 patent discloses an electronic module where one or more components, such as microcircuits, are embedded within an insulating layer. The invention focuses on creating solderless connections using first and second solid contact bumps that are metallurgically and electrically connected, for example, by ultrasonic or thermo-compression methods.

3. Grounds for Unpatentability

Ground 1: Obviousness over Nishiuma - Claims 1-2, 4-6, 11-13, 15-16, 19, 21, 25, and 27 are obvious over Nishiuma.

• Prior Art Relied Upon: Nishiuma (Patent 5,616,520).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Nishiuma discloses all limitations of the challenged claims. Nishiuma teaches a semiconductor integrated circuit device (an "electronic module") with a semiconductor chip (the "component") mounted on a wiring substrate. The substrate's surface wiring constitutes the "first conductive-pattern layer." Nishiuma’s solderless ball-bonding process, which uses gold (Au) balls bonded and flattened onto both the substrate and the chip, discloses the "first and second solid contact bumps." Finally, a ceramic dam frame surrounds and seals the chip, forming an "insulating-material layer" wherein the component is "embedded" and electrically connected as claimed.
  • Key Aspects: Nishiuma explicitly touts the reliability benefits of its solderless process, which avoids solder that is prone to thermal fatigue, directly aligning with the objectives of the ’527 patent.

Ground 2: Obviousness over Nishiuma and Nakatani - Claims 7-8 and 17-18 are obvious over Nishiuma in view of Nakatani.

• Prior Art Relied Upon: Nishiuma (Patent 5,616,520), Nakatani (Application # 2002/0159242).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner asserted that Nishiuma provides the foundational structure for an electronic module with a single embedded component. Nakatani was cited for its teaching of mounting a "plurality" of electronic components (e.g., surface acoustic wave devices) within a single module. The combination of Nishiuma's packaging technology with Nakatani's multi-component architecture allegedly renders obvious the claims reciting a "plurality of components."
  • Motivation to Combine: A POSITA would combine the teachings of Nishiuma and Nakatani to expand a module's capabilities and processing power while advancing the known industry goals of miniaturization and higher-density packaging. This combination was presented as a predictable application of known techniques to achieve expected results.
  • Expectation of Success: A POSITA would have a reasonable expectation of success, as both references describe conventional techniques for mounting and connecting IC chips within a sealed package, making their combination straightforward.

Ground 3: Obviousness over Yoneyama and Onda - Claims 1-27 are obvious over Yoneyama in view of Onda.

• Prior Art Relied Upon: Yoneyama (Japanese Patent Publication No. 2002-280713), Onda (Japanese Patent Publication No. 2001-085473).

• Core Argument for this Ground:

  • Prior Art Mapping: Petitioner argued that Yoneyama discloses a circuit board with embedded IC chips, an insulating layer, and conductive layers. Yoneyama connects the IC chips to a conductive layer using gold bumps ("second solid contact bumps"). Petitioner contended that a POSITA would look to Onda to improve this connection. Onda teaches a dual-bump connection scheme, using "tower bumps" on the wiring substrate ("first solid contact bumps") that connect to bumps on the semiconductor chip. This combined structure allegedly meets all limitations of the independent claims.
  • Motivation to Combine: A POSITA would combine Yoneyama's embedded chip structure with Onda's dual-bump connection method for several known benefits taught by Onda. These include improving the device's resistance to thermal stress, increasing connection strength, and simplifying the manufacturing process for electrically connecting the components.
  • Expectation of Success: Success would be expected because implementing Onda's conventional dual-bump connection technique in Yoneyama's embedded module structure involves the application of known technologies to solve well-understood problems in semiconductor packaging.

• Additional Grounds: Petitioner asserted additional obviousness challenges, including claims 20 and 26 over Nishiuma, Nakatani, and Yoneyama (for adding memory circuits) and claims 3 and 14 over Nishiuma and Shibata (for adding layered bumps to improve bonding).

4. Arguments Regarding Discretionary Denial

• Petitioner argued against discretionary denial under §325(d), asserting that the primary prior art references (Nishiuma, Nakatani, Shibata, Yoneyama, and Onda) were never considered or cited during the original prosecution of the ’527 patent and offer new, distinct teachings.
• Petitioner also argued that denial under §314(a) based on Fintiv factors is unwarranted. The parallel district court litigation was described as being in its infancy, with a motion to transfer pending. Petitioner asserted that the Board's Final Written Decision would likely issue months before the median time-to-trial in the current venue, and the petition's strong merits outweigh any potential inefficiencies of parallel proceedings.

5. Relief Requested

• Petitioner requests institution of an inter partes review and cancellation of claims 1-27 of the ’527 patent as unpatentable.