Apple Inc v. ImberaTek LLC

1. Case Identification

• Case #: IPR2025-00577
• Patent #: 7,732,909
• Filed: February 5, 2025
• Petitioner(s): Apple Inc.
• Patent Owner(s): ImberaTek LLC
• Challenged Claims: 1-33

2. Patent Overview

• Title: Method for Embedding a Component in a Base
• Brief Description: The ’909 patent discloses an electronic module and method where electronic components (microcircuits) are embedded within a hole in a baseboard. The structure includes conductive patterns, contact openings for electrical connections, and conductive material on the hole's sidewalls for electromagnetic interference (EMI) protection.

3. Grounds for Unpatentability

Ground 1: Claims 1-33 are obvious over McCormack in view of Eiji

• Prior Art Relied Upon: McCormack (Application # 2002/0175402) and Eiji (JP Application Publication # 2002-016327).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that McCormack taught all elements of the challenged claims except for the explicit use of conductive material on the sidewalls of a component-hosting cavity for EMI shielding. McCormack described a multi-layer printed circuit board with an embedded integrated electronic component in a cavity within a core substrate. It also disclosed forming contact openings through a dielectric layer to connect the component’s pads to external conductive patterns, using processes like electroless and electrolytic copper plating. Petitioner asserted that Eiji supplied the missing element by teaching the formation of a copper plating shielding layer on the inner surface of a through-hole used to embed electronic components. Eiji expressly stated this layer shields against electromagnetic waves, reduces noise, and stabilizes electrical characteristics. The combination, therefore, allegedly rendered every limitation of claims 1-33 obvious.
  • Motivation to Combine: Petitioner contended a person of ordinary skill in the art (POSITA) would combine McCormack and Eiji to improve the performance of McCormack’s embedded component design. A POSITA would have recognized that components in McCormack’s high-frequency applications are susceptible to EMI. Eiji provided a known solution to this exact problem—lining the component cavity with a conductive shield. A POSITA would combine these known elements to achieve the predictable result of a shielded, embedded component module with improved noise immunity and electrical stability.
  • Expectation of Success: A POSITA would have had a high expectation of success because both references described analogous circuit board manufacturing techniques. The proposed combination involved applying Eiji’s conventional shielding technique to McCormack’s known embedded component structure, which required no undue experimentation.

Ground 2: Claims 1-33 are obvious over Sakamoto in view of Eiji

• Prior Art Relied Upon: Sakamoto (JP Application Publication # 2001-339165A) and Eiji (JP Application Publication # 2002-016327).

• Core Argument for this Ground:

  • Prior Art Mapping: Petitioner argued that Sakamoto, like McCormack, taught a multilayer printed wiring substrate with a pre-embedded IC chip in a core substrate. Sakamoto disclosed an interlayer resin insulating layer over the chip, conductive circuits, and vias connecting the chip's pads to the circuits. It also taught using materials like glass epoxy for the substrate and forming conductive layers via electroless and electrolytic plating. Similar to the first ground, Petitioner asserted that Sakamoto taught all limitations except for the EMI shielding on the cavity sidewalls. Again, Petitioner relied on Eiji to teach this missing element. By adding Eiji's copper shielding layer to the inner surface of the recessed portion in Sakamoto's core substrate, the combination allegedly rendered all limitations of claims 1-33 obvious.
  • Motivation to Combine: The motivation was analogous to Ground 1. A POSITA would have been motivated to implement Eiji’s shielding layer in Sakamoto’s multilayer board to achieve known benefits consistent with Sakamoto’s own objectives of higher functionality and improved reliability. Adding EMI shielding would predictably reduce noise and stabilize electrical characteristics, particularly when multiple components are arranged in close proximity as taught by Sakamoto. This was presented as a straightforward application of a known technique (Eiji's shielding) to a known device (Sakamoto's board) to obtain predictable results.
  • Expectation of Success: Success was expected because the combination involved implementing a standard shielding technique into a similar and compatible circuit board architecture. Both Sakamoto and Eiji operated in the same field of semiconductor packaging, and the integration of a metal lining into a cavity was a routine and well-understood process.

• Additional Grounds: Petitioner asserted additional obviousness challenges, including grounds based on McCormack alone (claims 12-21, 23-27), Sakamoto alone (claims 12-27), McCormack and Eiji further in view of Sugaya (claims 12-27), and Sakamoto and Eiji further in view of Imoto (claims 12-27). These grounds relied on similar arguments, with Sugaya and Imoto providing further teachings on creating multi-layered structures by stacking multiple modules.

4. Arguments Regarding Discretionary Denial

• §325(d) - Advanced Bionics: Petitioner argued against denial, stating that the core prior art references (McCormack, Sakamoto, Eiji, Imoto) were never applied in a rejection during prosecution. While a family member of Sugaya was cited, it was not substantively applied. Therefore, the petition presented art and arguments materially different from those previously considered by the USPTO.
• §314(a) - Fintiv Factors: Petitioner contended that the Fintiv factors weighed in favor of institution. Petitioner argued that a co-pending district court case was in its early stages, a motion to transfer was pending, and the Board’s Final Written Decision (FWD) would likely issue months before any potential trial date. Petitioner asserted it filed the petition diligently and that the compelling merits of the multiple independent grounds for unpatentability outweighed any potential inefficiencies.

5. Relief Requested

• Petitioner requests institution of an inter partes review (IPR) and cancellation of claims 1-33 of Patent 7,732,909 as unpatentable under 35 U.S.C. §103.