Apple Inc v. ImberaTek LLC

1. Case Identification

• Case #: IPR2025-00578
• Patent #: 7,989,944
• Filed: February 6, 2025
• Petitioner(s): Apple Inc.
• Challenged Claims: 1-36

2. Patent Overview

• Title: Method For Embedding a Component in a Base
• Brief Description: The ’944 patent relates to circuit boards and electronic modules with embedded electronic components. The technology involves placing components, such as microcircuits, inside an insulating material layer between conductive pattern layers, which can form an electromagnetic interference (EMI) shield.

3. Grounds for Unpatentability

Ground 1: Obviousness over Sakamoto and Eiji - Claims 1-36

• Prior Art Relied Upon: Sakamoto (JP Application # 2001-339165A) and Eiji (JP Application # 2002-016327).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Sakamoto taught a multilayer printed wiring substrate with a built-in IC chip, disclosing the core limitations of claim 1, including an insulating layer, conductive pattern layers on first and second sides, a component embedded between them, a hardened insulating polymer layer over the component, and contact openings with conductors (vias). However, Sakamoto did not explicitly disclose a metal foil on the sidewalls of the component recess for EMI shielding. Petitioner asserted that Eiji remedied this by teaching a wiring substrate where a copper plating shield layer is formed on the inner surface of a through-hole used to embed electronic components. The combination of Sakamoto's multilayer structure with Eiji's EMI shielding allegedly rendered the claimed invention obvious.
  • Motivation to Combine: A POSITA would combine Eiji's shielding technique with Sakamoto’s multilayer board to achieve predictable benefits. Eiji explicitly taught that its shielding makes components "less susceptible to external electromagnetic waves" and helps "reduce the effects of noise." These known benefits would have motivated a POSITA to improve Sakamoto’s design, which sought higher functionality and reliability in densely packed electronics.
  • Expectation of Success: Petitioner contended a POSITA would have a reasonable expectation of success because both references described analogous multilayer wiring boards with embedded components. The proposed modification was the application of a known shielding technique from Eiji to a known board structure from Sakamoto to solve a known problem (EMI), yielding predictable results.

Ground 2: Obviousness over McCormack and Eiji - Claims 1-36

• Prior Art Relied Upon: McCormack (Application # 2002/0175402) and Eiji (JP Application # 2002-016327).

• Core Argument for this Ground:

  • Prior Art Mapping: Petitioner argued that McCormack disclosed a circuit board with an embedded integrated electronic component in a cavity within a core substrate. McCormack taught key claim elements, including an insulating material layer (core substrate and dielectric layers), first and second conductive pattern layers ("metal layers"), a component located in a hole, and a hardened insulating polymer layer ("dielectric layer 60") with contact openings. Similar to the first ground, Petitioner relied on Eiji to supply the teaching of a conductive EMI shield (metal foil) covering the sidewalls of the cavity where the component is embedded.
  • Motivation to Combine: A POSITA would be motivated to add Eiji’s EMI shielding to McCormack’s structure for the same reasons as in Ground 1: to protect against electromagnetic interference and stabilize the system's electrical characteristics. A secondary motivation was also presented: a POSITA would be motivated to use Eiji's teaching of a glass-epoxy resin composite material to enhance the mechanical strength of McCormack’s core substrate, a simple and well-known material choice for circuit boards.
  • Expectation of Success: Petitioner argued for a high expectation of success as the combination involved implementing a known solution (Eiji's EMI shield) to address a known problem in a similar, known device (McCormack’s board). The integration of a shield layer onto the sidewalls of a cavity was a straightforward modification for a POSITA.

• Additional Grounds: Petitioner asserted additional obviousness challenges based on three-reference combinations to address claims directed to multi-layered or stacked circuit boards. Ground 1B argued that claims 15-31 are obvious over Sakamoto, Eiji, and Imoto (JP Application # 2001-068624A), with Imoto providing the explicit teaching of stacking multiple substructures. Ground 2B argued that claims 15-31 are obvious over McCormack, Eiji, and Sugaya (Application # 2001/0030059), with Sugaya providing similar teachings for stacking modules to form a multi-layered structure.

4. Arguments Regarding Discretionary Denial

• §325(d) - Advanced Bionics Factors: Petitioner argued that discretionary denial under §325(d) was improper because none of the primary references (Sakamoto, McCormack, Eiji, Imoto) were applied in a rejection during the original prosecution of the ’944 patent. Petitioner contended this art was materially different from the art previously considered by the Examiner.
• §314(a) - Fintiv Factors: Petitioner argued that the Fintiv factors weighed in favor of institution. Key arguments included that a co-pending district court case was in its early stages, a motion to transfer was pending, and the Board's Final Written Decision would likely issue months before any potential trial date. Petitioner asserted it had been diligent in filing the petition and that the compelling merits of the invalidity grounds outweighed any potential inefficiencies.

5. Relief Requested

• Petitioner requests institution of an inter partes review and cancellation of claims 1-36 of the ’944 patent as unpatentable under 35 U.S.C. §103.