Apple Inc v. ImberaTek LLC

1. Case Identification

• Case #: IPR2025-00584
• Patent #: 11,716,816
• Filed: February 6, 2025
• Petitioner(s): Apple Inc.
• Patent Owner(s): ImberaTek LLC
• Challenged Claims: 1-14

2. Patent Overview

• Title: Method for Manufacturing an Electronic Module and Electronic Module
• Brief Description: The ’816 patent describes methods for fabricating electronic modules by embedding a component, such as a semiconductor chip, within an installation base like a circuit board. The process involves forming a recess in an insulating board that has a conductive layer, attaching the component within the recess, and subsequently forming conductive patterns.

3. Grounds for Unpatentability

Ground 1: Obviousness over Tsubosaki010 in view of Tsubosaki405 - Claims 1-14 are obvious over Tsubosaki010 in view of Tsubosaki405.

• Prior Art Relied Upon: Tsubosaki010 (Application # 2002/0180010) and Tsubosaki405 (Patent 5,714,405).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Tsubosaki010 discloses a multi-layered tape carrier package (TCP) structure that teaches nearly all limitations of the challenged claims. Specifically for independent claim 1, Tsubosaki010’s conductive leads (1c) and adhesive layer (1b) meet the "first conductive pattern layer" and "first insulating-material layer." The device hole (1a1) is the claimed "opening," and the embedded semiconductor chip (2) is the "component." An upper set of conductive leads in the stacked structure forms the "second conductive pattern layer," spaced from the lower leads by the adhesive layer (1b) and tape base (1a), which serves as the "second insulating-material layer." Tsubosaki010 further teaches that the conductive leads are formed on planar surfaces, meeting the "substantially planar" limitation.
  • Motivation to Combine: Petitioner contended that to the extent Tsubosaki010 does not explicitly describe its tape base and adhesive layers as insulating, a person of ordinary skill in the art (POSITA) would have been motivated to use insulating materials as taught by Tsubosaki405. Tsubosaki405 describes conventional carrier tapes with insulating base members and adhesives. A POSITA would combine these teachings to ensure electrical isolation between adjacent conductive leads in Tsubosaki010’s stacked structure, thereby preventing short circuits and ensuring proper module function.
  • Expectation of Success: A POSITA would have a high expectation of success, as Tsubosaki405’s teachings on insulating materials like polyimide represent a conventional and well-known approach for manufacturing the type of tape carrier structures disclosed in Tsubosaki010.

Ground 2: Obviousness over Tsubosaki010 Alone - Claims 1-14 are obvious over Tsubosaki010.

• Prior Art Relied Upon: Tsubosaki010 (Application # 2002/0180010).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner asserted that the same mapping of Tsubosaki010’s elements to the claim limitations from Ground 1 applies here.
  • Motivation to Combine (Rationale): As an alternative to Ground 1, Petitioner argued that the teachings of Tsubosaki405 were not necessary. A POSITA’s general background knowledge would have made the use of insulating materials for the tape base and adhesive layers obvious. Tsubosaki010 itself discloses the use of polyimide materials, which are commonly known insulators, making it obvious to use them for their insulating properties to achieve electrical isolation without reference to secondary prior art.

Ground 3: Obviousness over Oya in view of Shugg - Claims 1, 3-4, 6-8, 10-11, and 13-14 are obvious over Oya in view of Shugg.

• Prior Art Relied Upon: Oya (Application # 2004/0000710) and Shugg (a 1995 textbook, Handbook of Electrical and Electronic Insulating Materials).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner alleged that Oya discloses a multi-layered printed circuit board (PCB) with an embedded component that meets the core structure of the claims. For claim 1, Oya’s inner layer wiring (4) and substrate (7’) are the first conductive and insulating layers, respectively. The "hollow" (17) in Oya is the claimed "opening" containing the device (11) as the "component." Substrate (6’) is the second insulating layer, and the outer layer wiring (2) is the second conductive pattern layer. For claim 8, which requires a third insulating layer, Petitioner argued it would be obvious to add more layers to Oya’s PCB as taught by Shugg.
  • Motivation to Combine: A POSITA would combine Oya’s PCB structure with the general knowledge in the Shugg textbook. Shugg demonstrates that materials mentioned by Oya, such as epoxy resin and prepreg, were commonly used as insulators in electronic devices. The motivation would be to ensure electrical isolation between conductive wiring layers, reduce signal loss, and prevent cross-talk—all well-known problems addressed by using insulators. Furthermore, Shugg teaches layering PCB materials to form high-density circuits, motivating a POSITA to add a third insulating layer to Oya’s structure to realize the benefits of a more compact design.
  • Expectation of Success: A POSITA would have reasonably expected success in applying the fundamental principles and materials from Shugg to Oya's PCB design, as this would involve using known materials for their intended, predictable purpose.

4. Arguments Regarding Discretionary Denial

• §325(d) - Same or Substantially Same Art: Petitioner argued against discretionary denial under §325(d), asserting that the core prior art (Tsubosaki010, Tsubosaki405, and Shugg) was never cited or considered during the original prosecution of the ’816 patent. While Oya was listed in an Information Disclosure Statement (IDS), it was never substantively addressed by the Examiner. Therefore, the petition presented new, non-cumulative prior art and arguments that warrant review.
• §314(a) - Fintiv Factors: Petitioner argued that the Fintiv factors weigh against discretionary denial. The parallel district court litigation was in its infancy, a motion to transfer was pending, and the Board’s final written decision would likely issue months before the median time-to-trial in the current venue. Petitioner asserted it had filed the petition diligently and that the compelling merits of the unpatentability grounds outweigh any potential inefficiencies from parallel proceedings.

5. Relief Requested

• Petitioner requests institution of an inter partes review (IPR) and cancellation of claims 1-14 of the ’816 patent as unpatentable.