Kingston Technology Co Inc v. Vervain LLC

1. Case Identification

• Case #: IPR2025-00614
• Patent #: 8,891,298
• Filed: February 21, 2025
• Petitioner(s): Kingston Technology Company, Inc., Kingston Technology Corporation, and Kingston Digital, Inc.
• Patent Owner(s): Vervain, LLC
• Challenged Claims: 1-11

2. Patent Overview

• Title: Lifetime Mixed Level Non-Volatile Memory System
• Brief Description: The ’298 patent discloses a hybrid non-volatile memory system comprising distinct Single-Level Cell (SLC) and Multi-Level Cell (MLC) NAND flash memory modules. The system’s controller is adapted to preferentially direct data to the more robust SLC module upon either the failure of a data integrity test or as part of a wear-leveling strategy for frequently written data blocks.

3. Grounds for Unpatentability

Ground 1: Obviousness over Gavens - Claims 1-11 are obvious over Gavens in view of the knowledge of a POSITA.

• Prior Art Relied Upon: Gavens (Patent 8,634,240), its incorporated references, and general knowledge of a POSITA regarding wear-leveling techniques as exemplified by references like Sutardja and Moshayedi.
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Gavens disclosed a complete multi-modal NAND flash system with a controller managing both standard MLC memory and MLC memory operating in a lower-density, more robust binary mode (pseudo-SLC). Gavens taught multiple error management schemes, including performing a post-write read comparison (a "data integrity test") and, upon detecting excessive errors, rewriting a copy of the data to the more robust memory portion. Gavens also disclosed tracking the "age" of blocks by maintaining a "hot count" of erase/program cycles, which met the claim limitation of counting block accesses. While Gavens disclosed wear-leveling concepts, Petitioner contended that a POSITA would find it obvious to implement well-known wear-leveling techniques, such as transferring frequently written data to the more robust memory, to supplement Gavens’s error-management focus.
  • Motivation to Combine: A POSITA would be motivated to substitute a "real" SLC memory module for Gavens's pseudo-SLC portion to achieve superior endurance and performance, which was a known design trade-off. Furthermore, a POSITA would combine Gavens's error management with known wear-leveling techniques for the common and predictable purpose of avoiding premature system failure and improving overall memory lifetime.
  • Expectation of Success: A POSITA would have a high expectation of success in substituting a true SLC module, as it would operate with a standard NAND flash controller to achieve similar or better results. Combining error management and wear leveling was a common practice in NAND flash controller design.

Ground 2: Obviousness over Moshayedi - Claims 1-11 are obvious over Moshayedi in view of the knowledge of a POSITA.

• Prior Art Relied Upon: Moshayedi (Application # 2009/0327591) and general knowledge of a POSITA regarding error management techniques as exemplified by Gavens.

• Core Argument for this Ground:

  • Prior Art Mapping: Petitioner asserted that Moshayedi disclosed a hybrid memory system with a controller coupled to distinct SLC and MLC flash memory chips. Moshayedi’s controller performed wear leveling by tracking access frequency (via write counts for logical blocks and erase counts for physical blocks) and transferring frequently written "hot data" to the more robust SLC module, directly teaching the allocation limitation. To address the data integrity test, Moshayedi disclosed tracking data read errors for each block and relocating data from blocks with high error counts to blocks with "less wear," which a POSITA would understand to mean SLC blocks. This functionality, Petitioner argued, met the claimed limitation of remapping data to SLC upon failure of a data integrity test.
  • Motivation to Combine: The primary argument for this ground was that Moshayedi taught all limitations of claim 1. Alternatively, if the Board found Moshayedi's read-error management insufficient, Petitioner argued a POSITA, starting with Moshayedi’s advanced wear-leveling system, would be motivated to incorporate known and complementary error-management techniques, such as the post-write-read checks in Gavens, to further enhance system reliability and prevent premature failure.
  • Expectation of Success: A POSITA would have a high expectation of success, as integrating different but related data management techniques (wear leveling and error correction) was a routine aspect of designing robust flash memory controllers.

• Additional Grounds: Petitioner asserted an additional obviousness challenge against claims 1-11 over Sutardja (Application # 2008/0140918). This ground relied on similar arguments, contending Sutardja taught a hybrid SLC/MLC system with wear-leveling functions that moved frequently written data to SLC and a "degradation test" that remapped data from failing MLC blocks to the more robust SLC memory.

4. Key Claim Construction Positions

• "MLC non-volatile memory module" / "SLC non-volatile memory module": Petitioner argued that for the purposes of the petition, these terms should be construed as referring to distinct physical modules with different underlying circuitry, as a POSITA would understand. This construction was asserted to be critical because it distinguishes the claimed invention from prior art that merely operates a single MLC memory chip in a "pseudo-SLC" mode. Petitioner maintained that the ’298 patent’s specification and prosecution history supported this distinction between physically separate module types.
• "blocks": Petitioner noted that a district court had construed this term to mean "a physical group of memory cells." Petitioner maintained that its obviousness arguments were valid whether "blocks" were interpreted as physical blocks or logical blocks.

5. Arguments Regarding Discretionary Denial

• Petitioner argued that discretionary denial under §314(a) based on Fintiv factors would be inappropriate. The petition was presented as a "compelling, meritorious challenge" where the prior art would plainly lead to a conclusion of unpatentability. It was also argued that discovery in the parallel district court litigation was in its early stages, with minimal investment by the parties and the court, and that several of the challenged claims were not asserted in that litigation, reducing the overlap of issues.
• Petitioner also argued against denial under §325(d), stating that none of the primary prior art references (Gavens, Moshayedi, Sutardja) were before the Examiner during the original prosecution. Therefore, the art was not cumulative, and the arguments presented were materially different from those previously considered by the USPTO.

6. Relief Requested

• Petitioner requested the institution of an inter partes review and the cancellation of claims 1-11 of the ’298 patent as unpatentable.