Kingston Technology Co Inc v. Vervain LLC

1. Case Identification

• Case #: IPR2025-00616
• Patent #: 10,950,300
• Filed: February 21, 2025
• Petitioner(s): Kingston Technology Company, Inc., Kingston Technology Corporation, and Kingston Digital, Inc.
• Patent Owner(s): Vervain, LLC
• Challenged Claims: 1-12

2. Patent Overview

• Title: Lifetime Mixed Level Non-Volatile Memory System
• Brief Description: The ’300 patent relates to a non-volatile memory system architecture that combines multi-level cell (MLC) and single-level cell (SLC) NAND flash memory. The system uses a controller to manage data placement, perform data integrity tests, and implement wear-leveling strategies to enhance the operational lifetime and reliability of the memory device.

3. Grounds for Unpatentability

Ground 1: Claims 1-12 are obvious over Gavens in view of the knowledge of a POSITA.

• Prior Art Relied Upon: Gavens (Patent 8,634,240) and its incorporated references, combined with the general knowledge of a Person of Ordinary Skill in the Art (POSITA).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Gavens discloses a complete multi-modal NAND flash system that teaches the core limitations of the challenged claims. Gavens describes a memory controller managing an MLC memory array where portions can be configured to operate in a binary, "pseudo-SLC" (pSLC) mode, which offers higher endurance than standard MLC operation. Petitioner contended that Gavens also discloses the claimed "data integrity test" by teaching a post-write-read process where data written to the MLC portion is compared to a cached "original copy" stored in random access volatile memory (RAVM). If the number of errors exceeds a threshold, the original data is rewritten to the more robust pSLC portion. Petitioner asserted this process maps directly to the key features of independent claims 1 and 12, including using RAVM to retain data for comparison and remapping data to a higher-endurance region upon failure.
  • Motivation to Combine: Petitioner asserted that a POSITA would be motivated to substitute a "native" SLC memory module for the pSLC portion described in Gavens. This substitution represented a simple and predictable design choice aimed at further improving the endurance and performance of the memory system, leveraging the well-known benefits of native SLC memory over pSLC. The motivation arose from the ordinary goal of enhancing the lifetime and reliability of a flash memory system using known, interchangeable components for their established purposes.
  • Expectation of Success: A POSITA would have had a high expectation of success in making this substitution. Combining a Gavens-like memory management system with a native SLC module was a straightforward integration of existing technologies. This combination would predictably result in a more robust and longer-lasting memory system, as the operational principles of both the controller and the distinct memory types were well understood in the art.

4. Key Claim Construction Positions

• Petitioner argued that several key terms in the ’300 patent should be construed according to their established, technical meanings to a POSITA in the field of NAND flash memory, rather than the abstract definitions allegedly used to obscure the invention's relationship to the prior art.
• "Memory space": Petitioner proposed this term should be construed as the logical address space that is mapped by the controller to the physical memory elements. This construction was based on claim amendments made during prosecution that required memory elements to be "mapped" to their respective memory spaces, linking the abstract "space" to the function of logical-to-physical address mapping.
• "MLC/SLC memory element": Petitioner proposed these terms should be construed as physical, addressable blocks of NAND flash memory of their respective, distinct types (i.e., multi-bit per cell vs. single-bit per cell). This distinguishes them from individual storage cells, which are not independently addressable memory units.
• Petitioner contended these constructions are critical to the invalidity analysis because they demonstrate that the claims, when properly understood, describe a conventional hybrid flash memory architecture, making its obviousness in light of prior art like Gavens apparent.

5. Arguments Regarding Discretionary Denial

• Petitioner argued that discretionary denial under 35 U.S.C. §314(a) or §325(d) would be inappropriate.
• Fintiv Factors: The petition contended that the factors weigh against denial. The parallel district court litigation is in its early stages, with only preliminary contentions exchanged and no expert discovery, depositions, or final contentions. Further, the district court trial is scheduled for December 2025, providing ample time for a Final Written Decision (FWD) from the Board well before trial. Petitioner also argued the petition presents a compelling, meritorious challenge to the patent's validity.
• §325(d) Factors: Petitioner asserted that Gavens was not before the USPTO examiner during the prosecution of the ’300 patent. Accordingly, the arguments and references presented in the petition were not previously considered and are not cumulative to the prosecution record, making denial under §325(d) improper.

6. Relief Requested

• Petitioner requests the institution of an inter partes review and the cancellation of claims 1-12 of Patent 10,950,300 as unpatentable.