Kingston Technology Company, Inc., Kingston Technology Corporation, and Kingston Digital, Inc. v. Vervain, LLC

Petition

Petition summary

## 1. Case Identification
- Case Number: [IPR2025-00616](https://ai-lab.exparte.com/case/ptab/IPR2025-00616)
- Patent #: [10,950,300](https://ai-lab.exparte.com/patent/10950300)
- Filed: February 21, 2025
- Petitioner(s): [Kingston Technology Company, Inc.](https://ai-lab.exparte.com/party/kingston-technology-co-inc), [Kingston Technology Corporation](https://ai-lab.exparte.com/party/kingston-technology-co-inc), and Kingston Digital, Inc.
- Patent Owner(s): [Vervain, LLC](https://ai-lab.exparte.com/party/vervain-llc)
- Challenged Claims: 1-12

## 2. Patent Overview
- Title: Lifetime Mixed Level Non-Volatile Memory System
- Brief Description: The ’300 patent describes a memory system that combines Multi-Level Cell (MLC) and Single-Level Cell (SLC) non-volatile memory. The system uses a controller to manage data storage, including performing a data integrity test and remapping data to enhance system endurance and lifetime.

## 3. Grounds for Unpatentability

#### Ground 1: Obviousness over Gavens and Incorporated References - Claims 1-12 are obvious over Gavens in view of the knowledge of a POSITA.
  - **Prior Art Relied Upon:** Gavens (Patent 8,634,240), which incorporates by reference numerous other documents including Gorobets (Application # 2011/0153912), Paley (Application # 2010/0172180), and Harari (Patent 5,936,971). Petitioner also cited references like Lee (Patent 8,078,794), Sutardja (Application # 2008/0140918), and Moshayedi (Application # 2009/0327591) as evidence of a POSITA's knowledge.
  - **Core Argument for this Ground:**
    - **Prior Art Mapping:** Petitioner argued that the challenged claims are unpatentable over Gavens, which discloses a complete multi-modal NAND flash system with error management techniques. Although Gavens does not explicitly disclose a "pure" hybrid system with distinct SLC and MLC memory modules, it teaches partitioning a memory array to operate a portion in a high-endurance, single-bit "binary" or "pseudo-SLC" (pSLC) mode and another portion in a high-density MLC mode. Petitioner contended it would have been obvious to a person of ordinary skill in the art (POSITA) to substitute a well-known "native" SLC memory module for the pSLC portion of Gavens to achieve even greater, predictable endurance benefits.
    - **Prior Art Mapping (cont.):** Gavens was asserted to teach the claimed "data integrity test." It describes a post-write-read process where data written to the MLC portion is checked for errors "by comparison with the original copy which may be cached." If errors exceed a threshold, a copy of the original data is written to the more robust, lower-density (pSLC) portion. Petitioner argued this maps directly to the claimed test (comparing stored data to retained data in volatile memory) and the subsequent remapping upon failure. The incorporated references, such as Gorobets and Paley, were cited to provide explicit teachings of using Random Access Volatile Memory (RAVM) within a controller for caching and for maintaining Flash Translation Layer (FTL) address tables, satisfying other limitations of the independent claims. Dependent claims directed to specific features like flash memory (claim 4), DRAM/SRAM (claims 5-6), and wear leveling (claim 10) were argued to be inherent properties or well-known, obvious implementations within the hybrid system framework taught by the prior art.
    - **Motivation to Combine:** A POSITA would have been motivated to substitute a native SLC module into the Gavens system to leverage the well-known and superior endurance advantages of SLC memory over both MLC and pSLC memory. This was a common design trade-off to enhance system lifetime, which is the stated goal of the ’300 patent. The motivation to combine Gavens's error management with known wear-leveling techniques (e.g., from Lee or Sutardja) was to create a more robust and reliable memory system, a predictable goal in the field.
    - **Expectation of Success:** Combining native SLC and MLC modules with a controller managing data placement was a well-established architecture in the prior art. The components were standard, and their interaction was predictable. Therefore, a POSITA would have had a high expectation of success in implementing a native SLC module in the Gavens system to achieve the claimed invention without undue experimentation.

## 4. Key Claim Construction Positions
- **"MLC/SLC non-volatile memory" and "memory element":** Petitioner argued that in the context of the ’300 patent and the art, these terms should be construed based on their established technical meanings. "MLC non-volatile memory" refers to memory cells and circuitry capable of storing multiple logical pages in a single physical page, while "SLC non-volatile memory" refers to those incapable of doing so. The term "memory element" was argued to mean a physical, addressable memory block. These constructions were crucial to Petitioner's argument that the claims, despite their abstract language, read on known physical hardware disclosed in the prior art.
- **"memory space":** Petitioner contended that prosecution history established that "memory space" refers to a logical address space, which is mapped by the controller to the physical "memory elements" (MLC and SLC blocks). This construction was central to mapping the prior art's disclosure of logical-to-physical address management (a standard FTL function) onto the claim limitations.

## 5. Arguments Regarding Discretionary Denial
- **§314 (Fintiv Factors):** Petitioner argued against discretionary denial based on a co-pending district court action. It asserted the petition presents a "compelling, meritorious challenge" (Fintiv factor 6). It also argued that other factors favored institution: the district court case was in its early stages with minimal investment (factor 3); there was not a complete overlap of issues, as claim 6 was not asserted in the litigation (factor 4); and the trial date was distant, reducing concerns about timing (factor 2).
- **§325(d) (Same or Substantially the Same Art):** Petitioner argued that denial under §325(d) was inappropriate because the primary reference, Gavens, was not before the Examiner during the original prosecution of the ’300 patent. Petitioner contended that Gavens is materially different from the art considered by the Examiner and, therefore, the petition raises new patentability questions that warrant review.

## 6. Relief Requested
- Petitioner requested institution of an inter partes review and cancellation of claims 1-12 of the ’300 patent as unpatentable.

Kingston targets mixed non-volatile memory patent: Gavens prior art cited against all 12 claims as obvious for combining SLC/MLC for system lifetime.