PTAB

IPR2025-00683

Taiwan Semiconductor Mfg Co Ltd v. Advanced Integrated Circuit Process LLC

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petition

1. Case Identification

2. Patent Overview

  • Title: SEMICONDUCTOR DEVICE
  • Brief Description: The ’425 patent discloses a semiconductor device, particularly a metal-insulator-semiconductor field-effect transistor (MISFET), that includes a stress-relief film. This film is positioned between a silicon compound layer (e.g., SiGe in a source/drain region) and a sidewall spacer to mitigate performance degradation caused by stress from an overlying stress insulating film.

3. Grounds for Unpatentability

Ground 1: Obviousness over Wu and Alvarez - Claims 1, 3-5, 7-9, and 11-15 are obvious over [Wu](https://ai-lab.exparte.com/case/ptab/IPR2025-00683/doc/1005) in view of [Alvarez](https://ai-lab.exparte.com/case/ptab/IPR2025-00683/doc/1006).

  • Prior Art Relied Upon: Wu (Application # 2009/0246922), Alvarez (Application # 2007/0249069).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Wu discloses a strained CMOS transistor with all the basic structural elements of claim 1, including PMOS regions with raised SiGe source/drain layers that create compressive stress. Wu also discloses a contact etch stop layer (CESL) over the device which can be tensile or compressive. Wu’s process creates a gap between the SiGe layer and the gate sidewall spacer. Petitioner asserted this combination maps onto claim 1 by incorporating Alvarez's stress-controlling layer into the gap present in Wu's device to serve as the claimed "first stress-relief film."
    • Motivation to Combine: A Person of Ordinary Skill in the Art (POSITA) would combine the teachings to solve a known problem. A tensile CESL improves NMOS performance but can degrade the performance of PMOS devices. Alvarez teaches using a "stress-controlling" or "buffer" layer beneath a tensile CESL to mitigate these adverse effects on PMOS transistors. A POSITA would have been motivated to incorporate Alvarez’s stress-relief layer into Wu’s device to improve overall CMOS performance, selectively block silicide formation in certain regions, and streamline manufacturing.
    • Expectation of Success: A POSITA would have a reasonable expectation of success because adding Alvarez’s buffer layer (e.g., silicon oxide) into the gap in Wu's structure involves well-known deposition and patterning techniques. The combination uses known elements for their intended purposes to achieve predictable results in improving device performance.

Ground 2: Obviousness over Cheng - Claims 1, 3-9, and 11-12 are obvious over [Cheng](https://ai-lab.exparte.com/case/ptab/IPR2025-00683/doc/1008).

  • Prior Art Relied Upon: Cheng (Application # 2005/0112817).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner contended that Cheng, when properly interpreted, discloses every limitation of the challenged claims. Cheng describes a PMOS device with raised SiGe source/drain regions that create compressive stress and a tensile etch stop layer. Critically, Petitioner argued that Cheng’s disclosure of “dummy spacers” made of silicon dioxide (SiO2) located between the SiGe layer and the primary sidewall spacer meets the limitations of the "first stress-relief film."
    • Motivation to Combine (N/A - single reference): Cheng's dummy spacers are described as preventing tension from the tensile overlayer from adversely influencing carrier mobility in the pFET, which is precisely the purpose of the ’425 patent’s stress-relief film.
    • Expectation of Success (N/A - single reference): Not applicable.
    • Key Aspects: Petitioner's argument relies on a corrected interpretation of Cheng’s figures, which Petitioner asserts contain a rendering error. The corrected structure shows the epitaxial SiGe growing around, not replacing, the non-crystalline sidewalls, thereby creating the space for the dummy spacer to function as the claimed stress-relief film.

Ground 3: Obviousness over Saito, Fukutome, and James - Claims 1, 3-4, 7-8, and 10 are obvious over [Saito](https://ai-lab.exparte.com/case/ptab/IPR2025-00683/doc/1010) in view of [Fukutome](https://ai-lab.exparte.com/case/ptab/IPR2025-00683/doc/1011) and [James](https://ai-lab.exparte.com/case/ptab/IPR2025-00683/doc/1012).

  • Prior Art Relied Upon: Saito (Application # 2008/0029825), Fukutome (Application # 2005/0285203), and James (a 2005 IEEE conference paper).

  • Core Argument for this Ground:

    • Prior Art Mapping: Petitioner asserted that Saito discloses a conventional SRAM circuit structure. The proposed combination modifies Saito’s PMOS transistors by replacing their non-epitaxial source/drain layers with Fukutome’s raised, faceted epitaxial SiGe layers. This introduces compressive stress to improve PMOS performance. The combination further modifies Saito by making its blanket silicon nitride (SiN) insulating film a tensile CESL, as taught by James, to improve NMOS performance. Finally, Petitioner argued that an insulating film disclosed by Saito (film 10A), which forms in recesses and on sidewalls, would function as the claimed "stress-relief film" in the combined device, buffering the PMOS device from the tensile CESL.
    • Motivation to Combine: A POSITA would be motivated to combine these references to improve the performance of Saito's SRAM device using well-known, state-of-the-art techniques. Incorporating Fukutome’s raised SiGe was a standard method for boosting PMOS performance, and applying a tensile nitride layer as taught by James was a standard, inexpensive method for boosting NMOS performance.
    • Expectation of Success: A POSITA would expect success as these were all common, commercially proven techniques for improving transistor performance. The combination involved substituting known elements to achieve their predictable functions without requiring undue experimentation.

  • Additional Grounds: Petitioner asserted additional obviousness challenges, including combinations of Wu, Alvarez, and Wolf (a textbook) to address claim 2 (Ground 1B), and combinations of Cheng, Wang, and/or Wolf to address claim 2 and other claims (Grounds 2B-2D). These grounds relied on similar theories but added references to teach features like I-shaped offset spacers (from Wolf) or to corroborate teachings of raised SiGe (from Wang).

4. Key Technical Contentions (Beyond Claim Construction)

  • Interpretation of Cheng's Figures: A central contention is that Cheng’s figures (e.g., Fig. 4e) contain a rendering error. Petitioner argued that a POSITA would understand from Cheng’s text and general semiconductor fabrication principles that the epitaxial SiGe regions would grow selectively on crystalline surfaces, extending up and around the non-crystalline sidewall spacers, rather than replacing them as depicted. This corrected understanding is critical to Petitioner's argument that Cheng's "dummy spacer" exists in a space analogous to that of the claimed stress-relief film.
  • Interpretation of Saito's Figures: Petitioner argued that Saito's figures contain a clear clerical error, labeling a polysilicon gate in cross-section views as "5b" when it corresponds to "3c" in the top-down schematic. A POSITA would have immediately recognized and corrected this error, allowing for a proper understanding of the device structure.

5. Arguments Regarding Discretionary Denial

  • Petitioner argued discretionary denial under Fintiv is not warranted. To simplify the analysis, Petitioner stipulated that, if the IPR is instituted, it will not pursue in the related district court proceeding any ground that it raised or reasonably could have raised in the IPR. Petitioner asserted this stipulation weighs heavily against denial. Further, it argued that the co-pending litigation is in a very early stage, with no substantive orders issued and fact discovery having just begun, meaning judicial and party resources have not been significantly expended.

6. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-15 of the ’425 patent as unpatentable.