PTAB

IPR2025-00865

Taiwan Semiconductor Mfg Co Ltd v. Marlin Semiconductor Ltd

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Semiconductor Contact Structure
  • Brief Description: The ’747 patent relates to semiconductor manufacturing processes and structures. It purports to address drawbacks in prior art where a barrier layer is formed between upper and lower contact structures that are created in separate manufacturing steps.

3. Grounds for Unpatentability

Ground 1: Claims 1-5 and 8 are anticipated or obvious over Pethe

  • Prior Art Relied Upon: Pethe (Patent 9,461,143).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Pethe’s Figure 5B, which describes a MOSFET structure, discloses every limitation of independent claim 1. Specifically, Pethe was alleged to teach a semiconductor structure comprising a substrate (302), a first dielectric layer (region 323), at least two metal gates (308A-E), spacers with a truncated top surface (recessed spacers 520), a source/drain (S/D) region between the gates, a plurality of first contacts (trench contact vias 341A/B) connected to the S/D region, and a plurality of second contacts (gate contact vias 542A/B) connected to the metal gates. Petitioner further asserted that Pethe’s insulating cap layer (522) meets the "hard mask" limitation, with its top surface being on the same level as the first dielectric layer after planarization. The limitations of dependent claims 2-5 and 8 were also argued to be expressly or inherently disclosed.
    • Motivation to Combine (for §103 obviousness alternative): Petitioner argued that, to the extent any feature was not explicitly disclosed in a single embodiment, a person of ordinary skill in the art (POSITA) would have been motivated to combine the teachings from Pethe's various embodiments (e.g., Figures 3 and 5). This combination would have been logical because the figures share common features, labels, and design principles for fabricating MOSFETs.
    • Expectation of Success: A POSITA would have had a reasonable expectation of success in combining these teachings, as it involved the application of well-known semiconductor fabrication techniques to create predictable structures.

Ground 2: Claims 3, 8, and 9 are obvious over Chang in view of Huang

  • Prior Art Relied Upon: Chang (Application # 2006/0223302) and Huang (Application # 2013/0161707).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner asserted that Chang discloses the base semiconductor structure of claims 1-2, including an SRAM device with metal gates and self-aligned contacts. For claim 3, Huang’s disclosure of a Contact Etch Stop Layer (CESL 36) with a planarized, truncated top surface was argued to render the claimed "etching stop layer" obvious. For claims 8-9, Petitioner argued that Huang’s teaching of using a dual-damascene process to form higher-level metal interconnects (M0 vias and M1 lines) maps directly to the claimed "plurality of third contacts" that are monolithically formed and comprise a via hole and trace structure.
    • Motivation to Combine: A POSITA would combine Huang’s teachings with Chang’s device to achieve known improvements. First, a POSITA would add an etch stop layer as taught by Huang to Chang’s structure to solve the known problem of protecting underlying transistor features during contact etching. Second, a POSITA would incorporate Huang's multi-level metal interconnects to increase the device capacity and functional complexity of Chang’s SRAM, a primary and constant goal in semiconductor design. Using the dual-damascene technique taught by Huang was an industry-standard method for achieving this.
    • Expectation of Success: The proposed combination involved integrating standard, well-understood process modules (etch stop layers, back-end-of-line interconnects) into a conventional semiconductor device, leading to a predictable outcome.

Ground 3: Claim 7 is obvious over Pethe in view of Bohr

  • Prior Art Relied Upon: Pethe (Patent 9,461,143) and Bohr (Patent 8,436,404).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Pethe discloses all elements of claim 1, but not the additional limitation of claim 7, which requires a "salicide layer disposed between each S/D region and each first contact." Bohr was asserted to explicitly teach forming such a salicide layer between a source/drain diffusion region and a subsequently formed trench contact to improve device performance.
    • Motivation to Combine: A POSITA would have been motivated to incorporate Bohr's salicide layer into Pethe’s structure to achieve the well-known benefit of reducing electrical resistance at the contact interface, thereby improving transistor speed and efficiency. Petitioner also highlighted that Pethe and Bohr share a common assignee (Intel) and overlapping inventors, which it argued weighs in favor of finding a motivation to combine the references.
    • Expectation of Success: The formation of self-aligned silicide (salicide) layers was a conventional and predictable process in advanced semiconductor manufacturing, ensuring a high expectation of success.
  • Additional Grounds: Petitioner asserted additional obviousness challenges, including for claims 6-7 over Pethe alone, anticipation and obviousness for claims 1-2 over Chang alone, and further obviousness grounds based on combinations of Chang with Hong and Bohr.

4. Arguments Regarding Discretionary Denial

  • Petitioner argued that discretionary denial under Fintiv is inappropriate. The petition was filed expeditiously, just 23 days after a parallel ITC investigation was instituted. That ITC case was in its infancy, with no schedule set or substantive orders issued. Petitioner also noted that no other forum had adjudicated the patent claims and that several of the challenged claims in the IPR (claims 2-9) were not asserted in the ITC proceeding, weighing against denial.

5. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-9 of the ’747 patent as unpatentable.